Techniques for efficiently implementing totally self-checking checkers in MOS technology

N. K. Jha, J. A. Abraham

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


This paper presents some new techniques for reducing the transistor count oof MOS implementations of totally self-checking (TSC) checkers. The techniques are (1) transfer of fanouts, (2) removal of inverters and (3) use of multi-level realizations of functions. These techniques also increase the speed of the circuit and may reduce the number of required tests. Their effectiveness has been demonstrated by applying them to m-out-of-n and Berger code checkers. Impressive reductions of up to 90% in the transistor count in some cases have been obtained for the MOS implementation of these checkers. This directly translates into saving of chip area.

Original languageEnglish (US)
Pages (from-to)555-566
Number of pages12
JournalComputers and Mathematics with Applications
Issue number5-6
StatePublished - 1987
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Modeling and Simulation
  • Computational Theory and Mathematics
  • Computational Mathematics


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