TECHNIQUES FOR EFFICIENT MOS IMPLEMENTATION OF TOTALLY SELF-CHECKING CHECKERS.

Niraj K. Jha; Jacob A. Abraham

TECHNIQUES FOR EFFICIENT MOS IMPLEMENTATION OF TOTALLY SELF-CHECKING CHECKERS.

Niraj K. Jha, Jacob A. Abraham

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Some new techniques for reducing the transistor count of MOS implementations of totally self-checking (TSC) checker designs are presented. These techniques include transfer of fanouts, removal of inverters, and use of multilevel realizations of functions. They also increase the speed of the circuit and may reduce the number of required tests. Impressive reductions of up to 90% in the transistor count in some cases have been obtained for these MOS implementations. This directly translates into saving of chip area.

Original language	English (US)
Title of host publication	Digest of Papers - FTCS (Fault-Tolerant Computing Symposium)
Publisher	IEEE
Pages	430-435
Number of pages	6
ISBN (Print)	0818606185
State	Published - 1985
Externally published	Yes

Publication series

Name	Digest of Papers - FTCS (Fault-Tolerant Computing Symposium)
ISSN (Print)	0731-3071

All Science Journal Classification (ASJC) codes

Hardware and Architecture

Cite this

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title = "TECHNIQUES FOR EFFICIENT MOS IMPLEMENTATION OF TOTALLY SELF-CHECKING CHECKERS.",

abstract = "Some new techniques for reducing the transistor count of MOS implementations of totally self-checking (TSC) checker designs are presented. These techniques include transfer of fanouts, removal of inverters, and use of multilevel realizations of functions. They also increase the speed of the circuit and may reduce the number of required tests. Impressive reductions of up to 90% in the transistor count in some cases have been obtained for these MOS implementations. This directly translates into saving of chip area.",

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N2 - Some new techniques for reducing the transistor count of MOS implementations of totally self-checking (TSC) checker designs are presented. These techniques include transfer of fanouts, removal of inverters, and use of multilevel realizations of functions. They also increase the speed of the circuit and may reduce the number of required tests. Impressive reductions of up to 90% in the transistor count in some cases have been obtained for these MOS implementations. This directly translates into saving of chip area.

AB - Some new techniques for reducing the transistor count of MOS implementations of totally self-checking (TSC) checker designs are presented. These techniques include transfer of fanouts, removal of inverters, and use of multilevel realizations of functions. They also increase the speed of the circuit and may reduce the number of required tests. Impressive reductions of up to 90% in the transistor count in some cases have been obtained for these MOS implementations. This directly translates into saving of chip area.

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BT - Digest of Papers - FTCS (Fault-Tolerant Computing Symposium)

PB - IEEE

ER -

TECHNIQUES FOR EFFICIENT MOS IMPLEMENTATION OF TOTALLY SELF-CHECKING CHECKERS.

Abstract

Publication series

All Science Journal Classification (ASJC) codes

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