Some new techniques for reducing the transistor count of MOS implementations of totally self-checking (TSC) checker designs are presented. These techniques include transfer of fanouts, removal of inverters, and use of multilevel realizations of functions. They also increase the speed of the circuit and may reduce the number of required tests. Impressive reductions of up to 90% in the transistor count in some cases have been obtained for these MOS implementations. This directly translates into saving of chip area.