TECHNIQUES FOR EFFICIENT MOS IMPLEMENTATION OF TOTALLY SELF-CHECKING CHECKERS.

Niraj K. Jha, Jacob A. Abraham

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

Some new techniques for reducing the transistor count of MOS implementations of totally self-checking (TSC) checker designs are presented. These techniques include transfer of fanouts, removal of inverters, and use of multilevel realizations of functions. They also increase the speed of the circuit and may reduce the number of required tests. Impressive reductions of up to 90% in the transistor count in some cases have been obtained for these MOS implementations. This directly translates into saving of chip area.

Original languageEnglish (US)
Title of host publicationDigest of Papers - FTCS (Fault-Tolerant Computing Symposium)
PublisherIEEE
Pages430-435
Number of pages6
ISBN (Print)0818606185
StatePublished - Dec 1 1985
Externally publishedYes

Publication series

NameDigest of Papers - FTCS (Fault-Tolerant Computing Symposium)
ISSN (Print)0731-3071

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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  • Cite this

    Jha, N. K., & Abraham, J. A. (1985). TECHNIQUES FOR EFFICIENT MOS IMPLEMENTATION OF TOTALLY SELF-CHECKING CHECKERS. In Digest of Papers - FTCS (Fault-Tolerant Computing Symposium) (pp. 430-435). (Digest of Papers - FTCS (Fault-Tolerant Computing Symposium)). IEEE.