Abstract
Technology computer-aided design (TCAD)-assisted automation of structure synthesis followed by a transport-analysis-based capacitance extraction approach has been shown to have a significant potential in the recent past in terms of both accuracy and efficiency. In this brief, we first propose three methods to speedup TCAD-assisted capacitance extraction of an SRAM array layout, by partitioning the layout into several fragments. We demonstrate that the speedup of these partitioning methods, relative to that of TCAD-assisted full-array capacitance extraction method, can be as high as 17×, with an average of 3×. On the other hand, the error in capacitance derived using the partitioning methods can be as low as 1.01%, with an average of 4.93%. We apply the partitioning methods to several layout configurations and styles of FinFET SRAM array layouts and demonstrate their efficacy. We then apply the partitioning methods to a ring oscillator, register, and two-bit adder, and demonstrate similar results.
Original language | English (US) |
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Article number | 7047918 |
Pages (from-to) | 329-333 |
Number of pages | 5 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 24 |
Issue number | 1 |
DOIs | |
State | Published - Jan 2016 |
All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering
Keywords
- FinFET
- SRAM
- parasitic extraction
- structure synthesis
- technology computer-aided design (TCAD)