TY - JOUR
T1 - TCAD-Assisted Capacitance Extraction of FinFET SRAM and Logic Arrays
AU - Bhattacharya, Debajit
AU - Jha, Niraj K.
N1 - Funding Information:
This work was supported by the Directorate for Computer and Information Science and Engineering through the National Science Foundation under Grant CCF-1217076.
Publisher Copyright:
© 2015 IEEE.
PY - 2016/1
Y1 - 2016/1
N2 - Technology computer-aided design (TCAD)-assisted automation of structure synthesis followed by a transport-analysis-based capacitance extraction approach has been shown to have a significant potential in the recent past in terms of both accuracy and efficiency. In this brief, we first propose three methods to speedup TCAD-assisted capacitance extraction of an SRAM array layout, by partitioning the layout into several fragments. We demonstrate that the speedup of these partitioning methods, relative to that of TCAD-assisted full-array capacitance extraction method, can be as high as 17×, with an average of 3×. On the other hand, the error in capacitance derived using the partitioning methods can be as low as 1.01%, with an average of 4.93%. We apply the partitioning methods to several layout configurations and styles of FinFET SRAM array layouts and demonstrate their efficacy. We then apply the partitioning methods to a ring oscillator, register, and two-bit adder, and demonstrate similar results.
AB - Technology computer-aided design (TCAD)-assisted automation of structure synthesis followed by a transport-analysis-based capacitance extraction approach has been shown to have a significant potential in the recent past in terms of both accuracy and efficiency. In this brief, we first propose three methods to speedup TCAD-assisted capacitance extraction of an SRAM array layout, by partitioning the layout into several fragments. We demonstrate that the speedup of these partitioning methods, relative to that of TCAD-assisted full-array capacitance extraction method, can be as high as 17×, with an average of 3×. On the other hand, the error in capacitance derived using the partitioning methods can be as low as 1.01%, with an average of 4.93%. We apply the partitioning methods to several layout configurations and styles of FinFET SRAM array layouts and demonstrate their efficacy. We then apply the partitioning methods to a ring oscillator, register, and two-bit adder, and demonstrate similar results.
KW - FinFET
KW - SRAM
KW - parasitic extraction
KW - structure synthesis
KW - technology computer-aided design (TCAD)
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U2 - 10.1109/TVLSI.2015.2399358
DO - 10.1109/TVLSI.2015.2399358
M3 - Article
AN - SCOPUS:84961912374
SN - 1063-8210
VL - 24
SP - 329
EP - 333
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 1
M1 - 7047918
ER -