The increasing complexity of real-time embedded systems along with the short time-to-market for most of their applications have led designers to develop increasingly sophisticated algorithms and tools for system-level synthesis. At this level, coarse-grained tasks, such as discrete cosine transforms, are assigned and scheduled on general-purpose processors, field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). Hardware-software co-synthesis forms an important sub-problem of system-level synthesis in which price and power are frequently optimized under real-time constraints. This paper proposes a pre-processing step to aid system-level synthesis and is independent of both the targeted co-synthesis tool and its underlying algorithm. Experimental results show that using this methodology can reduce system price (power) by up to 84% (67%) and 12% (16%) on average while reducing co-synthesis tool run-time by 29%.
|Original language||English (US)|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - Jan 1 2002|
|Event||2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States|
Duration: May 26 2002 → May 29 2002
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering