Tao: Regular expression-based register-transfer level testability analysis and optimization

Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha

Research output: Contribution to journalArticle

26 Scopus citations

Abstract

In this paper, we present testability analysis and optimization (TAO), a novel methodology for register-transfer level (RTL) testability analysis and optimization of RTL controller/data path circuits. Unlike existing high-level testing techniques that cater restrictively to certain classes of circuits or design styles, TAO exploits the algebra of regular expressions to provide a unified framework for handling a wide variety of circuits including application-specific integrated circuits (ASICs), application-specific programmable processors (ASPPs), application-specific instruction processors (ASIPs), digital signal processors (DSPs), and microprocessors. We also augment TAO with a design-for-test (DFT) framework that can provide a low-cost testability solution by examining the tradeoffs in choosing from a diverse array of testability modifications like partial scan or test multiplexer insertion in different parts of the circuit. Test generation is symbolic and, hence, independent of bit width. Experimental results on benchmark circuits show that TAO is very efficient, in addition to being comprehensive. The fault coverage obtained is above 99% in all cases. The average area and delay overheads for incorporating testability into the benchmarks are only 3.2% and 1.0%, respectively. The test generation time is two-to-four orders of magnitude smaller than that associated with gate-level sequential test generators, while the test application times are comparable.

Original languageEnglish (US)
Pages (from-to)824-832
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume9
Issue number6
DOIs
StatePublished - Dec 1 2001

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Keywords

  • High-level test generation
  • Register-transfer level (RTL) test generation
  • Test synthesis
  • Testability analysis

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