TAO-BIST: a framework for testability analysis and optimization of RTL circuits for BIST

Srivaths Ravi, Niraj Kumar Jha, Ganesh Lakshminarayana

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

In this paper, we present TAO-BIST, a framework for testing register-transfer level (RTL) controller-datapath circuits using built-in self-test (BIST). Conventional BIST techniques at the RTL generally introduce more testability hardware than is necessary, thereby causing unnecessary area, delay and power overheads. They have typically been applied to only application-specific integrated circuits (ASICs). TAO-BIST adopts a three-phased approach to provide an efficient BIST framework at the RTL. In the first phase, we identify and add an initial set of test enhancements to the given circuit. In the second phase, we use regular-expression based high-level symbolic testability analysis of a BIST model of the circuit to completely encapsulate justification/propagation information for the modules under test. The regular expressions so obtained are then used to construct a Boolean function in the final phase for determining a test enhancement solution that meets delay constraints with minimal area overheads. Our method is applicable to a wide spectrum of circuits including ASICs, application-specific programmable processors (ASPPs), application-specific instruction processors (ASIPs), digital signal processors (DSPs) and microprocessors. Experimental results on a number of benchmark circuits show that high fault coverage (> 99%) can be obtained with our scheme. The average area and delay overheads due to TAO-BIST are only 6.0% and 1.5%, respectively. The test application time to achieve the high fault coverage for the whole controller-datapath circuit is also quite low.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE VLSI Test Symposium
PublisherIEEE
Pages398-406
Number of pages9
ISBN (Print)076950146X
StatePublished - Jan 1 1999
EventProceedings of the 1999 17th IEEE VLSI Test Symposium (VTS'99) - Dana Point, CA, USA
Duration: Apr 25 1999Apr 29 1999

Other

OtherProceedings of the 1999 17th IEEE VLSI Test Symposium (VTS'99)
CityDana Point, CA, USA
Period4/25/994/29/99

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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