Abstract
This paper uses a powerful three stage mapping methodology to realize highly concurrent systolic array processor architectures for image processing. The paper addresses the issues of designing special purpose systolic image enhancement processors for edge detection and median filtering and designing configurable general purpose systolic signal processors for Kalman filtering and artificial neural networks. The latter two arrays can then be specifically configured for image restoration and other image processing problems.
Original language | English (US) |
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Pages (from-to) | 308-320 |
Number of pages | 13 |
Journal | Proceedings of SPIE - The International Society for Optical Engineering |
Volume | 845 |
DOIs | |
State | Published - Oct 13 1987 |
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Computer Science Applications
- Applied Mathematics
- Electrical and Electronic Engineering