Synthesizing "verification aware" models: Why and how?

Malay K. Ganai, Akira Mukaiyama, Aarti Gupta, Kazutoshi Wakabayshi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Design-For-Verification (DFV) methodology i.e., exporting designer's intent to verification tools has been quite effective in improving verification efforts. We take one step further in improving the verification efforts, by separating the design optimized for performance, area and power from the design optimized for correctness, thereby reducing the verification burden. We propose a new paradigm Synthesis-For-Verification (SFV) which involves synthesizing "verification-aware" designs that are more suitable for functional verification. SFV methodology should be applied along with DFV methodology to obtain the full benefit of verification efforts. Note, this SFV paradigm requires support only from automated synthesis approaches, e.g. High Level Synthesis (HLS), and can be easily automated. This is in contrast to DFVmethodology, which requires designers' reliable insights. As part of SFV methodology, we first identify the effect of various design entities on the performance of model checkers. By guiding the use of such entities in existing behavioral synthesis techniques, we propose to obtain "verification friendly" models that are relatively easier to model check. We demonstrate effectiveness of such a paradigm using existing industry tools and designs.

Original languageEnglish (US)
Title of host publicationProceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems
Pages50-56
Number of pages7
DOIs
StatePublished - Dec 1 2007
Externally publishedYes
Event20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07 - Bangalore, India
Duration: Jan 6 2007Jan 10 2007

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
ISSN (Print)1063-9667

Other

Other20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07
CountryIndia
CityBangalore
Period1/6/071/10/07

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Synthesizing "verification aware" models: Why and how?'. Together they form a unique fingerprint.

  • Cite this

    Ganai, M. K., Mukaiyama, A., Gupta, A., & Wakabayshi, K. (2007). Synthesizing "verification aware" models: Why and how? In Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (pp. 50-56). [4092022] (Proceedings of the IEEE International Conference on VLSI Design). https://doi.org/10.1109/VLSID.2007.151