Synthesis of system-on-a-chip for testability

S. Ravi, N. K. Jha

Research output: Contribution to conferencePaperpeer-review


System synthesis takes an abstract system-level description as its input and produces a system-on-a-chip (SOC) as its output. Emphasis during synthesis is usually on optimizing one or more objectives such as price, area, performance and power. Testability enhancement of the SOC solution so obtained follows as a post-processing step to enable the application of precomputed test sequences to each embedded core and observe its responses. Unfortunately, cascading test synthesis to an SOC synthesis framework does not usually preserve the optimality of the solution obtained. The work presented here describes the first method that incorporates finite-state automata (FSA) based symbolic testability analysis within the framework of system synthesis to address the above shortcoming. Unlike many existing SOC test approaches, FSA based testability analysis facilitates low test overheads and test application times without sacrificing the test coverage of the embedded cores. Our experimental work with an existing multi-objective optimization algorithm and a system-level test framework for a number of examples indicate that efficient SOC architectures, which trade off different architectural features such as integrated circuit price, power consumption, area and/or testabiliy costs under real-time constraints, can be easily generated.

Original languageEnglish (US)
Number of pages8
StatePublished - 2001
Event14th International Conference on VLSI Design (VLSI DESIGN 2001) - Bangalore, India
Duration: Jan 3 2001Jan 7 2001


Other14th International Conference on VLSI Design (VLSI DESIGN 2001)

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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