Testing of sequential circuits is greatly facilitated by using scan techniques to directly control and observe the latches. Adding scan capability after logic synthesis may incur significant area and delay overheads. For such cases, we present a technique called synthesis for parallel partial scan in which latches are incrementally selected for partial scan based on some new structural analysis criteria that we introduce. Delay overhead is minimized, in most cases made zero or nearly zero, by judiciously selecting the latches in the non-critical paths. A heuristic is used to maximally merge the scan logic with the combinational logic of the sequential circuit to minimize the area overhead. The latches used in our scheme are normal, non-scan latches. Experimental results on ISCAS '89 benchmarks resynthesized by our method indicate that we can, in general, achieve the same level of testability with fewer latches selected for partial scan, as compared to previous methods based on structural analysis.