TY - GEN
T1 - Synthesis of sequential circuits for easy testability through performance-oriented parallel partial scan
AU - Bhatia, Sandeep
AU - Jha, Niraj K.
N1 - Copyright:
Copyright 2004 Elsevier B.V., All rights reserved.
PY - 1993
Y1 - 1993
N2 - Testing of sequential circuits is greatly facilitated by using scan techniques to directly control and observe the latches. Adding scan capability after logic synthesis may incur significant area and delay overheads. For such cases, we present a technique called synthesis for parallel partial scan in which latches are incrementally selected for partial scan based on some new structural analysis criteria that we introduce. Delay overhead is minimized, in most cases made zero or nearly zero, by judiciously selecting the latches in the non-critical paths. A heuristic is used to maximally merge the scan logic with the combinational logic of the sequential circuit to minimize the area overhead. The latches used in our scheme are normal, non-scan latches. Experimental results on ISCAS '89 benchmarks resynthesized by our method indicate that we can, in general, achieve the same level of testability with fewer latches selected for partial scan, as compared to previous methods based on structural analysis.
AB - Testing of sequential circuits is greatly facilitated by using scan techniques to directly control and observe the latches. Adding scan capability after logic synthesis may incur significant area and delay overheads. For such cases, we present a technique called synthesis for parallel partial scan in which latches are incrementally selected for partial scan based on some new structural analysis criteria that we introduce. Delay overhead is minimized, in most cases made zero or nearly zero, by judiciously selecting the latches in the non-critical paths. A heuristic is used to maximally merge the scan logic with the combinational logic of the sequential circuit to minimize the area overhead. The latches used in our scheme are normal, non-scan latches. Experimental results on ISCAS '89 benchmarks resynthesized by our method indicate that we can, in general, achieve the same level of testability with fewer latches selected for partial scan, as compared to previous methods based on structural analysis.
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M3 - Conference contribution
AN - SCOPUS:0027806822
SN - 0818642300
T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
SP - 151
EP - 154
BT - Proceedings - IEEE International Conference on Computer Design
A2 - Anon, null
PB - Publ by IEEE
T2 - Proceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Y2 - 3 October 1993 through 6 October 1993
ER -