@inproceedings{c7672dece6fc4eb18169270b6a9deb59,
title = "Synthesis of multi-level combinational circuits for complete robust path delay fault testability",
abstract = "Several synthesis rules for obtaining a multilevel multioutput logic circuit with 100% hazard-free robust testability of path delay faults are explored. In the simplest of these rules, an irredundant two-level implementation of the logic function, which is not robustly testable, is modified to a three-level or a four-level completely robust testable implementation. Algebraic factorization is applied to the modified implementation to obtain a completely robust testable multi level circuit at a relatively low area overhead. This rule was found to make most of the considered Berkeley programmable logic array (PLA) benchmark realizations completely testable. For a small number of cases where this synthesis rule is only partially applicable, another rule is presented, which can guarantee complete testability, but at a slightly higher area overhead. Both these synthesis rules also ensure testability of all multiple stuck-at faults with an easily derivable test set. Four other heuristic synthesis rules that can aid in obtaining a completely robust testable circuit at a lower area overhead in some cases are also presented.",
author = "Jha, {N. H.} and I. Pomeranz and Reddy, {S. M.} and Miller, {R. I.}",
year = "1992",
month = jan,
day = "1",
doi = "10.1109/FTCS.1992.243573",
language = "English (US)",
series = "FTCS 1992 - 22nd Annual International Symposium on Fault-Tolerant Computing",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "280--287",
booktitle = "FTCS 1992 - 22nd Annual International Symposium on Fault-Tolerant Computing",
address = "United States",
note = "22nd Annual International Symposium on Fault-Tolerant Computing, FTCS 1992 ; Conference date: 08-07-1992 Through 10-07-1992",
}