Synthesis of multi-level combinational circuits for complete robust path delay fault testability

N. H. Jha, I. Pomeranz, S. M. Reddy, R. I. Miller

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

Several synthesis rules for obtaining a multilevel multioutput logic circuit with 100% hazard-free robust testability of path delay faults are explored. In the simplest of these rules, an irredundant two-level implementation of the logic function, which is not robustly testable, is modified to a three-level or a four-level completely robust testable implementation. Algebraic factorization is applied to the modified implementation to obtain a completely robust testable multi level circuit at a relatively low area overhead. This rule was found to make most of the considered Berkeley programmable logic array (PLA) benchmark realizations completely testable. For a small number of cases where this synthesis rule is only partially applicable, another rule is presented, which can guarantee complete testability, but at a slightly higher area overhead. Both these synthesis rules also ensure testability of all multiple stuck-at faults with an easily derivable test set. Four other heuristic synthesis rules that can aid in obtaining a completely robust testable circuit at a lower area overhead in some cases are also presented.

Original languageEnglish (US)
Title of host publicationFTCS 1992 - 22nd Annual International Symposium on Fault-Tolerant Computing
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages280-287
Number of pages8
ISBN (Electronic)0818628758, 9780818628757
DOIs
StatePublished - Jan 1 1992
Event22nd Annual International Symposium on Fault-Tolerant Computing, FTCS 1992 - Boston, United States
Duration: Jul 8 1992Jul 10 1992

Publication series

NameFTCS 1992 - 22nd Annual International Symposium on Fault-Tolerant Computing

Conference

Conference22nd Annual International Symposium on Fault-Tolerant Computing, FTCS 1992
CountryUnited States
CityBoston
Period7/8/927/10/92

All Science Journal Classification (ASJC) codes

  • Software
  • Safety, Risk, Reliability and Quality
  • Hardware and Architecture

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    Jha, N. H., Pomeranz, I., Reddy, S. M., & Miller, R. I. (1992). Synthesis of multi-level combinational circuits for complete robust path delay fault testability. In FTCS 1992 - 22nd Annual International Symposium on Fault-Tolerant Computing (pp. 280-287). [243573] (FTCS 1992 - 22nd Annual International Symposium on Fault-Tolerant Computing). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FTCS.1992.243573