Synthesis of majority and minority networks and its applications to QCA, TPL and SET based nanotechnologies

Rui Zhang, Pallav Gupta, Niraj Kumar Jha

Research output: Contribution to journalConference article

44 Scopus citations

Abstract

In this paper, we present a methodology for efficient majority/minority network synthesis of arbitrary multi-output Boolean functions. Many emerging nanoscale technologies, such as quantum cellular automata (QCA), tunneling phase logic (TPL), and single electron tunneling (SET), are capable of implementing majority or minority logic very efficiently. However, there exists no comprehensive methodology or design automation tool for general multi-level majority/minority network synthesis. We have built the first such tool, Majority Logic Synthesizer (MALS), on top of an existing Boolean logic synthesis tool. We have performed experiments with 40 MCNC benchmarks. They indicate that up to 68.0% reduction in gate count is possible when utilizing majority logic, with the average reduction being 21.9%, compared to traditional logic synthesis, in which two-input AND/OR gates in the circuit are converted to majority gates.

Original languageEnglish (US)
Pages (from-to)229-234
Number of pages6
JournalProceedings of the IEEE International Conference on VLSI Design
StatePublished - Dec 1 2005
Event18th International Conference on VLSI Design: Power Aware Design of VLSI Systems - Kolkata, India
Duration: Jan 3 2005Jan 7 2005

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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