Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability

Steven M. Nowick, Niraj K. Jha, Fu Chiung Cheng

Research output: Contribution to journalArticlepeer-review

6 Scopus citations


In this paper, we present methods for synthesizing multilevel asynchronous circuits to be both hazard free and completely testable. Making an asynchronous two-level circuit hazard free usually requires the introduction of either redundant or nonprime cubes or both. This adversely affects the circuit's testability. However, using extra inputs, which is seldom necessary, and a synthesis-for-testability method, we convert the two-level circuit into a multilevel circuit that is completely testable. To avoid the addition of extra inputs as much as possible, we intro duce new exact minimization algorithms for hazard-free two-level logic where we flrst minimize the number of redundant cubes and then minimize the number of nonprime cubes. We target both the stuck-at and robust path delay fault models using similar methods. However, the area overhead for the latter may be slightly higher than for the former.

Original languageEnglish (US)
Pages (from-to)1514-1521
Number of pages8
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number12
StatePublished - 1997
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


Dive into the research topics of 'Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability'. Together they form a unique fingerprint.

Cite this