Presented are methods for synthesis of sequential circuits for easy testability based on a scheme previously referred to as 'synthesis for parallel scan'. A heuristic is used to achieve maximal merging of the testability logic with the normal combinational logic of the sequential circuit in order to minimize the area overhead. The latches used in the proposed scheme are normal nonscan latches. The synthesis for parallel scan scheme is applied to two different fault models. To facilitate stuck-at-fault testability of sequential circuits, the synthesis for parallel scan method is augmented with a novel structural analysis technique for selection of latches for partial scan with emphasis on minimization of delay overhead. A method for synthesizing fully hazard-free robust path-delay fault testable sequential circuits using the concept of synthesis for parallel scan is also presented.
|Original language||English (US)|
|Number of pages||16|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|State||Published - Feb 1996|
All Science Journal Classification (ASJC) codes
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering