Synthesis and optimization of threshold logic networks with application to nanotechnologies

Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceedingChapter

5 Scopus citations


We propose an algorithm for efficient threshold network synthesis of arbitrary multi-output Boolean functions. The main purpose of this work is to bridge the wide gap that currently exists between research on the development of nanoscale devices and research on the development of synthesis methodologies to generate optimized networks utilizing these devices. Many nanotechnologies, such as resonant tunneling diodes (RTD) and quantum cellular automata (QCA), are capable of implementing threshold logic. While functionally correct threshold gates have been successfully demonstrated, there exists no methodology or design automation tool for general multi-level threshold network synthesis. We have built the first such tool, ThrEshold Logic Synthesizer (TELS), on top of an existing Boolean logic synthesis tool. Experiments with about 60 multi-output benchmarks were performed, though the results of only 10 of them are reported in this paper because of space restrictions. They indicate that up to 77% reduction in gate count is possible when utilizing threshold logic, with an average reduction being 52%, compared to traditional logic synthesis. Furthermore, the synthesized networks are well-balanced, and hence delay-optimized.

Original languageEnglish (US)
Title of host publicationDesign, Automation, and Test in Europe
Subtitle of host publicationThe Most Influential Papers of 10 Years Date
PublisherSpringer Netherlands
Number of pages19
ISBN (Print)9781402064876
StatePublished - 2008

All Science Journal Classification (ASJC) codes

  • General Engineering


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