Synchronous versus asynchronous computation in very large scale integrated (VLSI) array processors

This paper compares timing and other aspects of a synchronous and asynchronous square array of processing elements, fabricated by means of VLSI technology. Timing models are developed for interprocessor communications and data transfer for both cases. The synchronous timing model emphasizes the clock skew phenomenon, and enables derivation of the dependence of the global clock period on the size of the array. This 0(N^∗∗3) dependence, along with the limited flexiblity with regards to programmability and extendability, call for a serious consideration of the asynchronous configuration. A self timed (asynchronous) model, based on the concept of wavefront oriented propagation of computation, is presented as an attractive alternative to the synchronous scheme. Some potential hazards, unique to the asynchronous model presented, and their solutions are also noted.