Synchronous versus asynchronous computation in very large scale integrated (VLSI) array processors

S. Y. Kung, R. J. Gal-Ezer

Research output: Contribution to journalConference articlepeer-review

20 Scopus citations


This paper compares timing and other aspects of a synchronous and asynchronous square array of processing elements, fabricated by means of VLSI technology. Timing models are developed for interprocessor communications and data transfer for both cases. The synchronous timing model emphasizes the clock skew phenomenon, and enables derivation of the dependence of the global clock period on the size of the array. This 0(N∗∗3) dependence, along with the limited flexiblity with regards to programmability and extendability, call for a serious consideration of the asynchronous configuration. A self timed (asynchronous) model, based on the concept of wavefront oriented propagation of computation, is presented as an attractive alternative to the synchronous scheme. Some potential hazards, unique to the asynchronous model presented, and their solutions are also noted.

Original languageEnglish (US)
Pages (from-to)53-65
Number of pages13
JournalProceedings of SPIE - The International Society for Optical Engineering
StatePublished - Dec 28 1982
Externally publishedYes
EventReal-Time Signal Processing V 1982 - Arlington, United States
Duration: May 5 1982May 7 1982

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Computer Science Applications
  • Applied Mathematics
  • Electrical and Electronic Engineering


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