Symmetric split-row LDPC decoders

Mohammad Shahrad, Mahdi Shabany

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

LDPC codes are deployed in many modern wired and wireless communication systems. While fully-parallel LDPC decoders are very efficient, they typically suffer from routing complexity. The Split-Row method effectively reduces this complexity with a minor performance loss. This paper shows the importance of symmetry in Split-Row architectures and proves that the implementation of Split-Row decoders based on new proposed smart column-permuted versions of parity check matrices leads to a better error performance as well as a more efficient hardware. Moreover, in order to achieve optimized column-permuted parity check matrices, a heuristic approach is proposed. This method is then generalized to support QC-LDPC codes. Applied to IEEE 802.3an (10GBASE-T Ethernet) and IEEE 802.11n (Wi-Fi) LDPC decoders, the new technique improves the error performance, while leading to almost 3x speed-up in the synthesis compile time and about 10% reduction in the critical path.

Original languageEnglish (US)
Title of host publicationIEEE International Symposium on Circuits and Systems
Subtitle of host publicationFrom Dreams to Innovation, ISCAS 2017 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467368520
DOIs
StatePublished - Sep 25 2017
Event50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States
Duration: May 28 2017May 31 2017

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
CountryUnited States
CityBaltimore
Period5/28/175/31/17

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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