SWIFT: Software implemented fault tolerance

George A. Reis, Jonathan Chang, Neil Vachharajani, Ram Rangan, David I. August

Research output: Chapter in Book/Report/Conference proceedingConference contribution

577 Scopus citations


To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. However, these advances make processors more susceptible to transient faults that can affect correctness. While reliable systems typically employ hardware techniques to address soft-errors, software techniques can provide a lower-cost and more flexible alternative. This paper presents a novel, software-only, transient-fault-detection technique, called SWIFT. SWIFT efficiently manages redundancy by reclaiming unused instruction-level resources present during the execution of most programs. SWIFT also provides a high level of protection and performance with an enhanced control-flow checking mechanism. We evaluate an implementation of SWIFT on an Itanium 2 which demonstrates exceptional fault coverage with a reasonable performance cost. Compared to the best known single-threaded approach utilizing an ECC memory system, SWIFT demonstrates a 51% average speedup.

Original languageEnglish (US)
Title of host publicationProceedings of the 2005 International Symposium on Code Generation and Optimization, CGO 2005
Number of pages12
StatePublished - 2005

Publication series

NameProceedings of the 2005 International Symposium on Code Generation and Optimization, CGO 2005

All Science Journal Classification (ASJC) codes

  • General Engineering


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