TY - GEN
T1 - SWIFT
T2 - Software implemented fault tolerance
AU - Reis, George A.
AU - Chang, Jonathan
AU - Vachharajani, Neil
AU - Rangan, Ram
AU - August, David I.
PY - 2005
Y1 - 2005
N2 - To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. However, these advances make processors more susceptible to transient faults that can affect correctness. While reliable systems typically employ hardware techniques to address soft-errors, software techniques can provide a lower-cost and more flexible alternative. This paper presents a novel, software-only, transient-fault-detection technique, called SWIFT. SWIFT efficiently manages redundancy by reclaiming unused instruction-level resources present during the execution of most programs. SWIFT also provides a high level of protection and performance with an enhanced control-flow checking mechanism. We evaluate an implementation of SWIFT on an Itanium 2 which demonstrates exceptional fault coverage with a reasonable performance cost. Compared to the best known single-threaded approach utilizing an ECC memory system, SWIFT demonstrates a 51% average speedup.
AB - To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. However, these advances make processors more susceptible to transient faults that can affect correctness. While reliable systems typically employ hardware techniques to address soft-errors, software techniques can provide a lower-cost and more flexible alternative. This paper presents a novel, software-only, transient-fault-detection technique, called SWIFT. SWIFT efficiently manages redundancy by reclaiming unused instruction-level resources present during the execution of most programs. SWIFT also provides a high level of protection and performance with an enhanced control-flow checking mechanism. We evaluate an implementation of SWIFT on an Itanium 2 which demonstrates exceptional fault coverage with a reasonable performance cost. Compared to the best known single-threaded approach utilizing an ECC memory system, SWIFT demonstrates a 51% average speedup.
UR - http://www.scopus.com/inward/record.url?scp=33646829087&partnerID=8YFLogxK
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U2 - 10.1109/CGO.2005.34
DO - 10.1109/CGO.2005.34
M3 - Conference contribution
AN - SCOPUS:33646829087
SN - 076952298X
SN - 9780769522982
T3 - Proceedings of the 2005 International Symposium on Code Generation and Optimization, CGO 2005
SP - 243
EP - 254
BT - Proceedings of the 2005 International Symposium on Code Generation and Optimization, CGO 2005
ER -