SUPREM 3. 5, PROCESS MODELING OF GALLIUM ARSENIDE.

M. D. Deal, S. E. Hansen, R. Anholt, S. Chou, J. D. Plummer, R. W. Dutton, T. W. Sigmon, D. A. Stevenson, C. R. Helms, J. C. Bravman

Research output: Contribution to journalConference article

4 Scopus citations

Abstract

A computer program has been developed to simulate processes used to manufacture digital GaAs integrated circuits. The processes modeled in this first version of the simulator include ion implantation, diffusion, and activation. The simulator includes a routine to calculate threshold voltage for a MESFET or JFET based on the simulated processing results and on substrate properties. Parameters for the models were derived from an extensive number of implantation and diffusion experiments, the major results of which are presented.

Original languageEnglish (US)
Pages (from-to)256-259
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
DOIs
StatePublished - 1987
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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    Deal, M. D., Hansen, S. E., Anholt, R., Chou, S., Plummer, J. D., Dutton, R. W., Sigmon, T. W., Stevenson, D. A., Helms, C. R., & Bravman, J. C. (1987). SUPREM 3. 5, PROCESS MODELING OF GALLIUM ARSENIDE. Technical Digest - International Electron Devices Meeting, 256-259. https://doi.org/10.1109/iedm.1987.191403