Supporting RTL flow compatibility in a microarchitecture-level design framework

Daniel Schwartz-Narbonne, Carven Chan, Yogesh Mahajan, Sharad Malik

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Current RTL-based design methodologies face significant scaling challenges related to the difficulty of designing, modifying, and verifying RTL. RTL contains primarily low level structural information about the design. In contrast, the microarchitecture-level is much closer to the specification level, making it an effective entry point for hardware design. The explicit description of the high-level units of work is also beneficial for verification. Currently used models for high level design have very complex semantics. In this paper, we present a microarchitectural modeling language with simpler semantics. We demonstrate that it results in a significantly simpler synthesis to Verilog, providing for integration with existing RTL flows. Moreover, the simple semantics of the model enable the generation of PSL assertions for functionally verifying correctness of the synthesis. We demonstrate the efficacy of this approach through two case-studies - -a router switch and a processor design. We synthesized both designs, and formally verified the synthesis using the generated assertions.

Original languageEnglish (US)
Title of host publicationEmbedded Systems Week 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009
Pages343-352
Number of pages10
DOIs
StatePublished - Dec 22 2009
EventEmbedded Systems Week 2009, ESWEEK 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009 - Grenoble, France
Duration: Oct 11 2009Oct 16 2009

Publication series

NameEmbedded Systems Week 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009

Other

OtherEmbedded Systems Week 2009, ESWEEK 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009
CountryFrance
CityGrenoble
Period10/11/0910/16/09

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Software

Keywords

  • Formal models
  • Hardware resources
  • Hierarchical design
  • Microarchitecture level
  • Transactions

Fingerprint Dive into the research topics of 'Supporting RTL flow compatibility in a microarchitecture-level design framework'. Together they form a unique fingerprint.

  • Cite this

    Schwartz-Narbonne, D., Chan, C., Mahajan, Y., & Malik, S. (2009). Supporting RTL flow compatibility in a microarchitecture-level design framework. In Embedded Systems Week 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009 (pp. 343-352). (Embedded Systems Week 2009 - 7th IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis, CODES+ISSS 2009). https://doi.org/10.1145/1629435.1629482