Sub-threshold design: The challenges of minimizing circuit energy

B. H. Calhoun; A. Wang; N. Verma; A. Chandrakasan

doi:10.1145/1165573.1165661

Sub-threshold design: The challenges of minimizing circuit energy

B. H. Calhoun, A. Wang, N. Verma, A. Chandrakasan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

27 Scopus citations

Abstract

In this paper, we identify the key challenges that oppose sub-threshold circuit design and describe fabricated chips that verify techniques for overcoming the challenges.

Original language	English (US)
Title of host publication	ISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design
Pages	366-368
Number of pages	3
DOIs	https://doi.org/10.1145/1165573.1165661
State	Published - 2006
Externally published	Yes
Event	ISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design - Tegernsee, Bavaria, Germany Duration: Oct 4 2006 → Oct 6 2006

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
Volume	2006
ISSN (Print)	1533-4678

Other

Other	ISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design
Country/Territory	Germany
City	Tegernsee, Bavaria
Period	10/4/06 → 10/6/06

All Science Journal Classification (ASJC) codes

General Engineering

Keywords

Dynamic voltage scaling
Low voltage memory
Process variations
Sub-threshold digital circuits
Sub-threshold logic

Access to Document

10.1145/1165573.1165661

Cite this

Calhoun, B. H., Wang, A., Verma, N., & Chandrakasan, A. (2006). Sub-threshold design: The challenges of minimizing circuit energy. In ISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design (pp. 366-368). (Proceedings of the International Symposium on Low Power Electronics and Design; Vol. 2006). https://doi.org/10.1145/1165573.1165661

@inproceedings{e053dc2295eb45ff946640d41b3a6596,

title = "Sub-threshold design: The challenges of minimizing circuit energy",

abstract = "In this paper, we identify the key challenges that oppose sub-threshold circuit design and describe fabricated chips that verify techniques for overcoming the challenges.",

keywords = "Dynamic voltage scaling, Low voltage memory, Process variations, Sub-threshold digital circuits, Sub-threshold logic",

author = "Calhoun, {B. H.} and A. Wang and N. Verma and A. Chandrakasan",

year = "2006",

doi = "10.1145/1165573.1165661",

language = "English (US)",

isbn = "1595934626",

series = "Proceedings of the International Symposium on Low Power Electronics and Design",

pages = "366--368",

booktitle = "ISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design",

note = "ISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design ; Conference date: 04-10-2006 Through 06-10-2006",

}

Calhoun, BH, Wang, A, Verma, N & Chandrakasan, A 2006, Sub-threshold design: The challenges of minimizing circuit energy. in ISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design. Proceedings of the International Symposium on Low Power Electronics and Design, vol. 2006, pp. 366-368, ISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design, Tegernsee, Bavaria, Germany, 10/4/06. https://doi.org/10.1145/1165573.1165661

Sub-threshold design: The challenges of minimizing circuit energy. / Calhoun, B. H.; Wang, A.; Verma, N. et al.
ISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design. 2006. p. 366-368 (Proceedings of the International Symposium on Low Power Electronics and Design; Vol. 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Sub-threshold design

T2 - ISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design

AU - Calhoun, B. H.

AU - Wang, A.

AU - Verma, N.

AU - Chandrakasan, A.

PY - 2006

Y1 - 2006

N2 - In this paper, we identify the key challenges that oppose sub-threshold circuit design and describe fabricated chips that verify techniques for overcoming the challenges.

AB - In this paper, we identify the key challenges that oppose sub-threshold circuit design and describe fabricated chips that verify techniques for overcoming the challenges.

KW - Dynamic voltage scaling

KW - Low voltage memory

KW - Process variations

KW - Sub-threshold digital circuits

KW - Sub-threshold logic

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T3 - Proceedings of the International Symposium on Low Power Electronics and Design

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BT - ISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design

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ER -

Sub-threshold design: The challenges of minimizing circuit energy

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

Keywords

Access to Document

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