Sub-threshold design: The challenges of minimizing circuit energy

B. H. Calhoun, A. Wang, N. Verma, A. Chandrakasan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

22 Scopus citations

Abstract

In this paper, we identify the key challenges that oppose sub-threshold circuit design and describe fabricated chips that verify techniques for overcoming the challenges.

Original languageEnglish (US)
Title of host publicationISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design
Pages366-368
Number of pages3
DOIs
StatePublished - Dec 1 2006
Externally publishedYes
EventISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design - Tegernsee, Bavaria, Germany
Duration: Oct 4 2006Oct 6 2006

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
Volume2006
ISSN (Print)1533-4678

Other

OtherISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design
CountryGermany
CityTegernsee, Bavaria
Period10/4/0610/6/06

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Fingerprint Dive into the research topics of 'Sub-threshold design: The challenges of minimizing circuit energy'. Together they form a unique fingerprint.

  • Cite this

    Calhoun, B. H., Wang, A., Verma, N., & Chandrakasan, A. (2006). Sub-threshold design: The challenges of minimizing circuit energy. In ISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design (pp. 366-368). (Proceedings of the International Symposium on Low Power Electronics and Design; Vol. 2006). https://doi.org/10.1145/1165573.1165661