Structural simulation for architecture exploration

David I. August, Veerle Desmet, Sylvain Girbal, Daniel Gracia Pérez, Olivier Temam

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

While processor architecture design is currently more an art than a systematic process, growing complexity and more stringent time-to-market constraints are strong incentives for streamlining architecture design into a more systematic process. Methods have emerged for quickly scanning the large ranges of hardware block parameters. But, at the moment, systematic exploration rarely goes beyond such parametric design space exploration. We want to show that it is possible to move beyond parametric exploration to structural exploration, where different architecture blocks are automatically composed together, largely broadening the scope of design space exploration. For that purpose, we introduce a simulation environment, called UNISIMUNISIM, which is geared toward interoperability. UNISIMUNISIM achieves this goal with a combination of modular software development, distributed communication protocolscommunication protocols, a set of simulator service APIs, architecture communications interfaces (ACIs), and an open library/repository for providing a consistent set of simulator components. We illustrate the approach with the design exploration of the on-chip memory subsystem of an embedded processor target. Besides design space exploration design-space exploration, we also show that structural simulation can significantly ease the process of fairly and quantitatively comparing research ideas and illustrate that point with the comparison of state-of-the-art cache techniques. Finally, we disseminate the whole approach for both facilitating design space exploration design-space exploration and the fair comparison of research ideas through ArchExplorerArchExplorer, an atypical web-based infrastructure, where researchers and engineers can contribute and evaluate architecture ideas.

Original languageEnglish (US)
Title of host publicationProcessor and System-on-Chip Simulation
PublisherSpringer US
Pages85-104
Number of pages20
ISBN (Print)9781441961747
DOIs
StatePublished - Dec 1 2010

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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