Stream multicore processors

Michael Bedford Taylor; Walter Lee; Jason Eric Miller; David Wentzlaff; Ian Bratt; Ben Greenwald; Henry Hoffmann; Paul Johnson; Jason Kim; James Psota; Arvind Saraf; Nathan Shnidman; Volker Strumpen; Matt Frank; Rodric Rabbah; Saman Amarasinghe; Anant Agarwal

doi:10.1007/978-1-4020-5530-0_14

Stream multicore processors

Michael Bedford Taylor, Walter Lee, Jason Eric Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jason Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matt Frank, Rodric Rabbah, Saman Amarasinghe, Anant Agarwal

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

The physical realities of wire delay and power consumption seriously challenge the ability of microprocessor designers to continue designing monolithic architectures with centralized resources. Materials and process changes have proven insufficient to solve the fundamental physics problems, and it is increasingly challenging for existing architectures to turn chip resources into higher performance, at tractable costs. Fast moving VLSI technology will soon offer tens of billions of transistors, massive chip-level wire bandwidth for local interconnect, and a modestly larger number of pins. Processors need to convert the abundant chip-level resources into powerefficient application performance, while mitigating the negative effects of wire delays.

Original language	English (US)
Title of host publication	Processor Design
Subtitle of host publication	System-on-Chip Computing for ASICs and FPGAs
Publisher	Springer Netherlands
Pages	309-338
Number of pages	30
ISBN (Print)	9781402055294
DOIs	https://doi.org/10.1007/978-1-4020-5530-0_14
State	Published - 2007
Externally published	Yes

All Science Journal Classification (ASJC) codes

General Engineering

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10.1007/978-1-4020-5530-0_14

Cite this

Taylor, M. B., Lee, W., Miller, J. E., Wentzlaff, D., Bratt, I., Greenwald, B., Hoffmann, H., Johnson, P., Kim, J., Psota, J., Saraf, A., Shnidman, N., Strumpen, V., Frank, M., Rabbah, R., Amarasinghe, S., & Agarwal, A. (2007). Stream multicore processors. In Processor Design: System-on-Chip Computing for ASICs and FPGAs (pp. 309-338). Springer Netherlands. https://doi.org/10.1007/978-1-4020-5530-0_14

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abstract = "The physical realities of wire delay and power consumption seriously challenge the ability of microprocessor designers to continue designing monolithic architectures with centralized resources. Materials and process changes have proven insufficient to solve the fundamental physics problems, and it is increasingly challenging for existing architectures to turn chip resources into higher performance, at tractable costs. Fast moving VLSI technology will soon offer tens of billions of transistors, massive chip-level wire bandwidth for local interconnect, and a modestly larger number of pins. Processors need to convert the abundant chip-level resources into powerefficient application performance, while mitigating the negative effects of wire delays.",

author = "Taylor, {Michael Bedford} and Walter Lee and Miller, {Jason Eric} and David Wentzlaff and Ian Bratt and Ben Greenwald and Henry Hoffmann and Paul Johnson and Jason Kim and James Psota and Arvind Saraf and Nathan Shnidman and Volker Strumpen and Matt Frank and Rodric Rabbah and Saman Amarasinghe and Anant Agarwal",

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doi = "10.1007/978-1-4020-5530-0_14",

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Taylor, MB, Lee, W, Miller, JE, Wentzlaff, D, Bratt, I, Greenwald, B, Hoffmann, H, Johnson, P, Kim, J, Psota, J, Saraf, A, Shnidman, N, Strumpen, V, Frank, M, Rabbah, R, Amarasinghe, S & Agarwal, A 2007, Stream multicore processors. in Processor Design: System-on-Chip Computing for ASICs and FPGAs. Springer Netherlands, pp. 309-338. https://doi.org/10.1007/978-1-4020-5530-0_14

TY - CHAP

T1 - Stream multicore processors

AU - Taylor, Michael Bedford

AU - Lee, Walter

AU - Miller, Jason Eric

AU - Wentzlaff, David

AU - Bratt, Ian

AU - Greenwald, Ben

AU - Hoffmann, Henry

AU - Johnson, Paul

AU - Kim, Jason

AU - Psota, James

AU - Saraf, Arvind

AU - Shnidman, Nathan

AU - Strumpen, Volker

AU - Frank, Matt

AU - Rabbah, Rodric

AU - Amarasinghe, Saman

AU - Agarwal, Anant

PY - 2007

Y1 - 2007

N2 - The physical realities of wire delay and power consumption seriously challenge the ability of microprocessor designers to continue designing monolithic architectures with centralized resources. Materials and process changes have proven insufficient to solve the fundamental physics problems, and it is increasingly challenging for existing architectures to turn chip resources into higher performance, at tractable costs. Fast moving VLSI technology will soon offer tens of billions of transistors, massive chip-level wire bandwidth for local interconnect, and a modestly larger number of pins. Processors need to convert the abundant chip-level resources into powerefficient application performance, while mitigating the negative effects of wire delays.

AB - The physical realities of wire delay and power consumption seriously challenge the ability of microprocessor designers to continue designing monolithic architectures with centralized resources. Materials and process changes have proven insufficient to solve the fundamental physics problems, and it is increasingly challenging for existing architectures to turn chip resources into higher performance, at tractable costs. Fast moving VLSI technology will soon offer tens of billions of transistors, massive chip-level wire bandwidth for local interconnect, and a modestly larger number of pins. Processors need to convert the abundant chip-level resources into powerefficient application performance, while mitigating the negative effects of wire delays.

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DO - 10.1007/978-1-4020-5530-0_14

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SN - 9781402055294

SP - 309

EP - 338

BT - Processor Design

PB - Springer Netherlands

ER -

Stream multicore processors

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All Science Journal Classification (ASJC) codes

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