Stream multicore processors

Michael Bedford Taylor, Walter Lee, Jason Eric Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jason Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matt Frank, Rodric Rabbah, Saman Amarasinghe, Anant Agarwal

Research output: Chapter in Book/Report/Conference proceedingChapter


The physical realities of wire delay and power consumption seriously challenge the ability of microprocessor designers to continue designing monolithic architectures with centralized resources. Materials and process changes have proven insufficient to solve the fundamental physics problems, and it is increasingly challenging for existing architectures to turn chip resources into higher performance, at tractable costs. Fast moving VLSI technology will soon offer tens of billions of transistors, massive chip-level wire bandwidth for local interconnect, and a modestly larger number of pins. Processors need to convert the abundant chip-level resources into powerefficient application performance, while mitigating the negative effects of wire delays.

Original languageEnglish (US)
Title of host publicationProcessor Design
Subtitle of host publicationSystem-on-Chip Computing for ASICs and FPGAs
PublisherSpringer Netherlands
Number of pages30
ISBN (Print)9781402055294
StatePublished - 2007
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • General Engineering


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