The physical realities of wire delay and power consumption seriously challenge the ability of microprocessor designers to continue designing monolithic architectures with centralized resources. Materials and process changes have proven insufficient to solve the fundamental physics problems, and it is increasingly challenging for existing architectures to turn chip resources into higher performance, at tractable costs. Fast moving VLSI technology will soon offer tens of billions of transistors, massive chip-level wire bandwidth for local interconnect, and a modestly larger number of pins. Processors need to convert the abundant chip-level resources into powerefficient application performance, while mitigating the negative effects of wire delays.
|Original language||English (US)|
|Title of host publication||Processor Design|
|Subtitle of host publication||System-on-Chip Computing for ASICs and FPGAs|
|Number of pages||30|
|State||Published - 2007|
All Science Journal Classification (ASJC) codes