Statistical timing optimization of combinational logic circuits

High performance circuit design is becoming increasingly important in VLSI design. The most important problem faced in the design of these circuits is to meet a certain performance level. In the past few years CAD algorithms and tools have been well developed that improve the performance of logic circuits in the sense that the worst case delay is minimized. However, manufacturers recognize that worst case delay models are typically pessimistic and the manufactured ICs will have a range of performances reflecting the manufacturing variations. Thus, the real problem that needs to be solved in the performance optimization of these circuits is to maximize the percentage of fabricated circuits that will achieve a certain performance level, as opposed to minimizing the worst case delay which has been the focus thus far. In this paper we develop methods to improve the statistical timing behavior of a combinational logic circuit, given probability distributions for the gate and wire delays. This work uses a statistical timing analysis technique developed earlier to drive timing optimization in the right direction to achieve a prescribed goal with the least area overhead.