TY - JOUR
T1 - Statistical optimization of FinFET processor architectures under PVT variations using dual device-Type assignment
AU - Yu, Ye
AU - Jha, Niraj K.
N1 - Funding Information:
This work was supported by the National Science Foundation under Grant No. CCF-1318603. Authors’ addresses: Y. Yu and N. K. Jha, Electrical Engineering Department, Princeton University, Princeton, NJ 08544; email: {yeyu, jha}@princeton.edu. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies show this notice on the first page or initial screen of a display along with the full citation. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works requires prior specific permission and/or a fee. Permissions may be requested from Publications Dept., ACM, Inc., 2 Penn Plaza, Suite 701, New York, NY 10121-0701 USA, fax + 1 (212) 869-0481, or permissions@acm.org. © 2017 ACM 1550-4832/2017/09-ART3 $15.00 https://doi.org/10.1145/3110714
Publisher Copyright:
© 2017 ACM.
PY - 2017/9
Y1 - 2017/9
N2 - With semiconductor technology scaling to the 22nm node and beyond, fin field-effect transistor (FinFET) has started replacing complementary metal-oxide semiconductor (CMOS), thanks to its superior control of short-channel effects and much lower leakage current. However, process, supply voltage, and temperature (PVT) variations across the integrated circuit (IC) become worse with technology scaling. Thus, to analyze timing, leakage power, and dynamic power under PVT variations, statistical analysis/optimization techniques are more suitable than traditional static timing/power analysis and optimization counterparts. In this article, we propose a statistical optimization framework using dual device-Type assignment at the architecture level under PVT variations that takes spatial correlations into account and leverages circuit-level statistical analysis techniques. To the best of our knowledge, this is the first work to study statistical optimization at the system level under PVT variations. Simulation results show that leakage power yield and dynamic power yield at the mean value of the baseline can be improved by up to 44.2% and 21.2%, respectively, with no loss in timing yield for a single-core processor and up to 43.0% and 50.0%, respectively, without any loss in timing yield for an 8-core chip multiprocessor (CMP), at little area overhead. Under the same (99.0%) power yield constraints, leakage power and dynamic power are reduced by up to 91.2% and 4.3%, respectively, for a singlecore processor, and up to 44.6% and 12.5%, respectively, for an 8-core CMP,with no loss in timing yield.We also show that optimizations performed without taking module-To-module and core-To-core spatial correlations into account overestimate yield, establishing the importance of taking such correlations into account.
AB - With semiconductor technology scaling to the 22nm node and beyond, fin field-effect transistor (FinFET) has started replacing complementary metal-oxide semiconductor (CMOS), thanks to its superior control of short-channel effects and much lower leakage current. However, process, supply voltage, and temperature (PVT) variations across the integrated circuit (IC) become worse with technology scaling. Thus, to analyze timing, leakage power, and dynamic power under PVT variations, statistical analysis/optimization techniques are more suitable than traditional static timing/power analysis and optimization counterparts. In this article, we propose a statistical optimization framework using dual device-Type assignment at the architecture level under PVT variations that takes spatial correlations into account and leverages circuit-level statistical analysis techniques. To the best of our knowledge, this is the first work to study statistical optimization at the system level under PVT variations. Simulation results show that leakage power yield and dynamic power yield at the mean value of the baseline can be improved by up to 44.2% and 21.2%, respectively, with no loss in timing yield for a single-core processor and up to 43.0% and 50.0%, respectively, without any loss in timing yield for an 8-core chip multiprocessor (CMP), at little area overhead. Under the same (99.0%) power yield constraints, leakage power and dynamic power are reduced by up to 91.2% and 4.3%, respectively, for a singlecore processor, and up to 44.6% and 12.5%, respectively, for an 8-core CMP,with no loss in timing yield.We also show that optimizations performed without taking module-To-module and core-To-core spatial correlations into account overestimate yield, establishing the importance of taking such correlations into account.
KW - Chip multiprocessor
KW - FinFET
KW - PVT variations
KW - Statistical analysis
KW - Statistical optimization
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U2 - 10.1145/3110714
DO - 10.1145/3110714
M3 - Article
AN - SCOPUS:85030214301
SN - 1550-4832
VL - 14
JO - ACM Journal on Emerging Technologies in Computing Systems
JF - ACM Journal on Emerging Technologies in Computing Systems
IS - 1
M1 - 3
ER -