Statistical delay modeling in logic design and synthesis

Horng Fei Jyu, Sharad Malik

Research output: Contribution to journalConference article

11 Scopus citations

Abstract

Manufacturing disturbances are inevitable in the fabrication of integrated circuits. These disturbances will result in variations in the delay specifications of manufactured circuits. In order to capture the impact of these variations on the delay behavior of these circuits we propose a pair of statistical delay models for use in logic design. These models abstract the real variations from the process level and can be used for statistical delay analysis and optimization in logic design and synthesis while offering an efficiency vs. accuracy tradeoff.

Original languageEnglish (US)
Pages (from-to)126-130
Number of pages5
JournalProceedings - Design Automation Conference
DOIs
StatePublished - 1994
EventProceedings of the 31st Design Automation Conference - San Diego, CA, USA
Duration: Jun 6 1994Jun 10 1994

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering

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