Statistical delay modeling in logic design and synthesis

Manufacturing disturbances are inevitable in the fabrication of integrated circuits. These disturbances will result in variations in the delay specifications of manufactured circuits. In order to capture the impact of these variations on the delay behavior of these circuits we propose a pair of statistical delay models for use in logic design. These models abstract the real variations from the process level and can be used for statistical delay analysis and optimization in logic design and synthesis while offering an efficiency vs. accuracy tradeoff.