In this paper, we address the problem of state encoding of finite-state machines (FSMs) targeting threshold and majority logic based implementations, which have applications in nanotechnologies. Previous work on state encoding is based on Boolean logic. These methods try to optimize either the literal count or sum-of-product (SOP) terms count, which are more relevant for CMOS technology based circuits. As progress is made in the material and physical understanding of nanoscale devices, functionally-correct nanoscale circuits based on threshold and majority gates are being successfully demonstrated. However, there exists no methodology or design automation tool for state encoding targeting threshold and majority gate based implementations. We propose such a methodology based on an evolutionary algorithm. Experimental results indicate that large reductions in gate count, area and interconnect count are possible, compared to some traditional state encoding methods.