SRAM-based NATURE: A Dynamically reconfigurable FPGA based on 10T low-power SRAMs

Ting Jung Lin, Wei Zhang, Niraj K. Jha

Research output: Contribution to journalArticle

11 Scopus citations

Abstract

We presented a hybrid CMOS/nanotechnology reconfigurable architecture (NATURE), earlier. It was based on CMOS logic and nano RAMs. It used the concept of temporal logic folding and fine-grain (e.g., cycle-level) dynamic reconfiguration to increase logic density by an order of magnitude. This dynamic reconfiguration is done intra-circuit rather than inter-circuit. However, the previous design of NATURE required fine-grained distribution of nano RAMs throughout the field-programmable gate array (FPGA) architecture. Since the fabrication process of nano RAMs is not mature yet, this prevents immediate exploitation of NATURE. In this paper, we present a NATURE architecture that is based on CMOS logic and CMOS SRAMs that are used for on-chip dynamic reconfiguration. We use fast and low-power SRAM blocks that are based on 10T SRAM cells. We have also laid out the various FPGA components in a 65-nm technology to evaluate the FPGA performance. We hide the dynamic reconfiguration delay behind the computation delay through the use of shadow SRAM cells. Experimental results show more than an order of magnitude improvement in logic density and 3.48 × improvement in the area-delay product relative to a traditional baseline FPGA architecture that does not use the concept of logic folding.

Original languageEnglish (US)
Article number6060944
Pages (from-to)2151-2156
Number of pages6
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume20
Issue number11
DOIs
StatePublished - Jan 1 2012

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Keywords

  • Field-programmable gate arrays (FPGAs)
  • integrated circuits
  • logic folding
  • nanotechnology reconfigurable architecture (NATURE)

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