TY - GEN
T1 - Spice
T2 - Speculative Parallel Iteration Chunk Execution
AU - Raman, Easwaran
AU - Vachharajani, Neil
AU - Rangan, Ram
AU - August, David I.
PY - 2008
Y1 - 2008
N2 - The recent trend in the processor industry of packing multiple processor cores in a chip has increased the importance of automatic techniques for extracting thread level parallelism. A promising approach for extracting thread level parallelism in general purpose applications is to apply memory alias or value speculation to break dependences amongst threads and executes them concurrently. In this work, we present a speculative parallelization technique called Speculative Parallel Iteration Chunk execution (Spice) which relies on a novel software-only value prediction mechanism. Our value prediction technique predicts the loop live-ins of only a few iterations of a given loop, enabling speculative threads to start from those iterations. It also increases the probability of successful speculation by only predicting that the values will be used as live-ins in some future iterations of the loop. These twin properties enable our value prediction scheme to have high prediction accuracies while exposing significant coarse-grained thread-level parallelism. Spice has been implemented as an automatic transformation in a research compiler. The technique results in up to 157% speedup (101% on average) with 4 threads.
AB - The recent trend in the processor industry of packing multiple processor cores in a chip has increased the importance of automatic techniques for extracting thread level parallelism. A promising approach for extracting thread level parallelism in general purpose applications is to apply memory alias or value speculation to break dependences amongst threads and executes them concurrently. In this work, we present a speculative parallelization technique called Speculative Parallel Iteration Chunk execution (Spice) which relies on a novel software-only value prediction mechanism. Our value prediction technique predicts the loop live-ins of only a few iterations of a given loop, enabling speculative threads to start from those iterations. It also increases the probability of successful speculation by only predicting that the values will be used as live-ins in some future iterations of the loop. These twin properties enable our value prediction scheme to have high prediction accuracies while exposing significant coarse-grained thread-level parallelism. Spice has been implemented as an automatic transformation in a research compiler. The technique results in up to 157% speedup (101% on average) with 4 threads.
KW - Automatic paralleization
KW - Multicore architectures
KW - Speculative parallelization
KW - Thread level parallelism
KW - Value speculation
UR - http://www.scopus.com/inward/record.url?scp=43449123064&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=43449123064&partnerID=8YFLogxK
U2 - 10.1145/1356058.1356082
DO - 10.1145/1356058.1356082
M3 - Conference contribution
AN - SCOPUS:43449123064
SN - 9781595939784
T3 - Proceedings of the 2008 CGO - Sixth International Symposium on Code Generation and Optimization
SP - 175
EP - 184
BT - Proceedings of the 2008 CGO - Sixth International Symposium on Code Generation and Optimization
ER -