TY - GEN
T1 - SpFlow
T2 - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
AU - Nie, Qi
AU - Malik, Sharad
N1 - Publisher Copyright:
© 2019 IEEE
PY - 2019
Y1 - 2019
N2 - To improve the performance of sparse matrix-matrix multiplication (SpMM) running on a specialized architecture, orchestrating a data flow that maximizes data reuse in local memory is critical but challenging due to the irregular non-zero element locations and the wide range of sparsity. In this work, we proposed SpFlow, a memory-driven data flow optimization framework for SpMM. SpFlow can realize 54X fewer DRAM accesses and 97X fewer SRAM accesses on average than a GPU running the cuSPARSE kernel. And in comparison with a state-of-the-art accelerator, the performance can be improved by 3X, and SRAM accesses reduced by 5X on average.
AB - To improve the performance of sparse matrix-matrix multiplication (SpMM) running on a specialized architecture, orchestrating a data flow that maximizes data reuse in local memory is critical but challenging due to the irregular non-zero element locations and the wide range of sparsity. In this work, we proposed SpFlow, a memory-driven data flow optimization framework for SpMM. SpFlow can realize 54X fewer DRAM accesses and 97X fewer SRAM accesses on average than a GPU running the cuSPARSE kernel. And in comparison with a state-of-the-art accelerator, the performance can be improved by 3X, and SRAM accesses reduced by 5X on average.
UR - http://www.scopus.com/inward/record.url?scp=85066812084&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85066812084&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2019.8702111
DO - 10.1109/ISCAS.2019.8702111
M3 - Conference contribution
AN - SCOPUS:85066812084
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 26 May 2019 through 29 May 2019
ER -