To improve the performance of sparse matrix-matrix multiplication (SpMM) running on a specialized architecture, orchestrating a data flow that maximizes data reuse in local memory is critical but challenging due to the irregular non-zero element locations and the wide range of sparsity. In this work, we proposed SpFlow, a memory-driven data flow optimization framework for SpMM. SpFlow can realize 54X fewer DRAM accesses and 97X fewer SRAM accesses on average than a GPU running the cuSPARSE kernel. And in comparison with a state-of-the-art accelerator, the performance can be improved by 3X, and SRAM accesses reduced by 5X on average.
|Title of host publication
|2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
|Institute of Electrical and Electronics Engineers Inc.
|Published - 2019
|2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan
Duration: May 26 2019 → May 29 2019
|Proceedings - IEEE International Symposium on Circuits and Systems
|2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
|5/26/19 → 5/29/19
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering