Speculative parallelization using software multi-threaded transactions

Arun Raman, Hanjun Kim, Thomas R. Mason, Thomas B. Jablin, David I. August

Research output: Chapter in Book/Report/Conference proceedingConference contribution

61 Scopus citations

Abstract

With the right techniques, multicore architectures may be able to continue the exponential performance trend that elevated the performance of applications of all types for decades. While many scientific programs can be parallelized without speculative techniques, speculative parallelism appears to be the key to continuing this trend for general-purpose applications. Recently-proposed code parallelization techniques, such as those by Bridges et al. and by Thies et al., demonstrate scalable performance on multiple cores by using speculation to divide code into atomic units (transactions) that span multiple threads in order to expose data parallelism. Unfortunately, most software and hardware Thread-Level Speculation (TLS) memory systems and transactional memories are not sufficient because they only support single-threaded atomic units. Multi-threaded Transactions (MTXs) address this problem, but they require expensive hardware support as currently proposed in the literature. This paper proposes a Software MTX (SMTX) system that captures the applicability and performance of hardware MTX, but on existing multicore machines. The SMTX system yields a harmonic mean speedup of 13.36x on native hardware with four 6-core processors (24 cores in total) running speculatively parallelized applications.

Original languageEnglish (US)
Title of host publicationASPLOS XV - 15th International Conference on Architectural Support for Programming Languages and Operating Systems
Pages65-76
Number of pages12
DOIs
StatePublished - May 19 2010
Event15th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS XV - Pittsburgh, PA, United States
Duration: Mar 13 2010Mar 17 2010

Publication series

NameInternational Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Other

Other15th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS XV
CountryUnited States
CityPittsburgh, PA
Period3/13/103/17/10

All Science Journal Classification (ASJC) codes

  • Software
  • Information Systems
  • Hardware and Architecture

Keywords

  • Automatic parallelization
  • Loop-level parallelism
  • Multi-threaded transactions
  • Pipelined parallelism
  • Software transactional memory
  • Thread-level speculation

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