Transaction-level modeling is used in hardware design for describing designs at a higher level compared to the register-transfer level (RTL) (e.g. Cai and Gajski in CODES + ISSS '03: proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pp. 19-24, 2003; Chen et al. in FMCAD '07: proceedings of the formal methods in computer aided design, pp. 53-61, 2007; Mahajan et al. in MEMOCODE '07: proceedings of the 5th IEEE/ACM international conference on formal methods and models for codesign, pp. 123-132, 2007; Swan in DAC '06: proceedings of the 43rd annual conference on design automation, pp. 90-92, 2006). Each transaction represents a unit of work, which is also a useful unit for design verification. In such models, there are many properties of interest which involve interactions between multiple transactions. Examples of this are ordering relationships in sequential processing and hazard checking in pipelined circuits. Writing such properties on the RTL design requires significant expertise in understanding the higher-level computation being done in a given RTL design and possible instrumentation of the RTL to express the property of interest. This is a barrier to the easy use of such properties in RTL designs. In this paper, we consider specification of interaction properties at the transaction-level and the subsequent encoding of the property and the transaction-level model as a finite-state system for model checking.We discuss how the encoded finite-state system can be automatically generated from the specification of the property and the transaction-level model, and illustrate this through simple examples.
All Science Journal Classification (ASJC) codes
- Theoretical Computer Science
- Hardware and Architecture