Special purpose array processor implementation of neural networks

S. Y. Kung; John Vlontzos

Special purpose array processor implementation of neural networks

S. Y. Kung, John Vlontzos

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A universal digital VLSI design for implementing artificial neural networks is proposed. The design is based on a unified iterative neural network model. An implementation based on a combination of custom-built and commercially available chips is presented. In addition, a software environment for the array processor is discussed.

Original language	English (US)
Title of host publication	Proc 2 Int IEEE Conf Tools Artif Intell
Publisher	Publ by IEEE
Pages	130-137
Number of pages	8
ISBN (Print)	0818620846
State	Published - 1990
Event	Proceedings of the 2nd International IEEE Conference on Tools for Artificial Intelligence - Herndon, VA, USA Duration: Nov 6 1990 → Nov 9 1990

Publication series

Name	Proc 2 Int IEEE Conf Tools Artif Intell

Other

Other	Proceedings of the 2nd International IEEE Conference on Tools for Artificial Intelligence
City	Herndon, VA, USA
Period	11/6/90 → 11/9/90

All Science Journal Classification (ASJC) codes

General Engineering

Cite this

@inproceedings{0b3eaa4505104f208a945ab336947df9,

title = "Special purpose array processor implementation of neural networks",

abstract = "A universal digital VLSI design for implementing artificial neural networks is proposed. The design is based on a unified iterative neural network model. An implementation based on a combination of custom-built and commercially available chips is presented. In addition, a software environment for the array processor is discussed.",

author = "Kung, {S. Y.} and John Vlontzos",

year = "1990",

language = "English (US)",

isbn = "0818620846",

series = "Proc 2 Int IEEE Conf Tools Artif Intell",

publisher = "Publ by IEEE",

pages = "130--137",

booktitle = "Proc 2 Int IEEE Conf Tools Artif Intell",

note = "Proceedings of the 2nd International IEEE Conference on Tools for Artificial Intelligence ; Conference date: 06-11-1990 Through 09-11-1990",

}

TY - GEN

T1 - Special purpose array processor implementation of neural networks

AU - Kung, S. Y.

AU - Vlontzos, John

PY - 1990

Y1 - 1990

N2 - A universal digital VLSI design for implementing artificial neural networks is proposed. The design is based on a unified iterative neural network model. An implementation based on a combination of custom-built and commercially available chips is presented. In addition, a software environment for the array processor is discussed.

AB - A universal digital VLSI design for implementing artificial neural networks is proposed. The design is based on a unified iterative neural network model. An implementation based on a combination of custom-built and commercially available chips is presented. In addition, a software environment for the array processor is discussed.

UR - http://www.scopus.com/inward/record.url?scp=0025562893&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0025562893&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0025562893

SN - 0818620846

T3 - Proc 2 Int IEEE Conf Tools Artif Intell

SP - 130

EP - 137

BT - Proc 2 Int IEEE Conf Tools Artif Intell

PB - Publ by IEEE

T2 - Proceedings of the 2nd International IEEE Conference on Tools for Artificial Intelligence

Y2 - 6 November 1990 through 9 November 1990

ER -

Special purpose array processor implementation of neural networks

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

Other files and links

Fingerprint

Cite this