Special purpose array processor implementation of neural networks

S. Y. Kung, John Vlontzos

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A universal digital VLSI design for implementing artificial neural networks is proposed. The design is based on a unified iterative neural network model. An implementation based on a combination of custom-built and commercially available chips is presented. In addition, a software environment for the array processor is discussed.

Original languageEnglish (US)
Title of host publicationProc 2 Int IEEE Conf Tools Artif Intell
PublisherPubl by IEEE
Pages130-137
Number of pages8
ISBN (Print)0818620846
StatePublished - Dec 1 1990
EventProceedings of the 2nd International IEEE Conference on Tools for Artificial Intelligence - Herndon, VA, USA
Duration: Nov 6 1990Nov 9 1990

Publication series

NameProc 2 Int IEEE Conf Tools Artif Intell

Other

OtherProceedings of the 2nd International IEEE Conference on Tools for Artificial Intelligence
CityHerndon, VA, USA
Period11/6/9011/9/90

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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