TY - GEN
T1 - Sparse matrix to matrix multiplication
T2 - 30th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2019
AU - Malik, Sharad
AU - Golnari, Pareesa Ameneh
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - Accelerators for sparse matrix multiplication are important components in emerging systems. In this paper, we study the main challenges of accelerating Sparse Matrix Multiplication (SpMM). For the situations that data is not stored in the desired order (row/column order), we propose a compact high performance sparse format, which allows for random access to a dataset with low memory access overhead. We show that using this format results in a 14-49 times speedup for SpMM. Next, we propose a high performance systolic architecture for SpMM, which uses a mesh of comparators to locate the useful (non-zero) computation. This design maximizes data reuse by sharing the input data among a row/column of the mesh. We also show that, with similar memory access assumptions, the proposed architecture results in a 9-30 times speedup in comparison with the state of the art.
AB - Accelerators for sparse matrix multiplication are important components in emerging systems. In this paper, we study the main challenges of accelerating Sparse Matrix Multiplication (SpMM). For the situations that data is not stored in the desired order (row/column order), we propose a compact high performance sparse format, which allows for random access to a dataset with low memory access overhead. We show that using this format results in a 14-49 times speedup for SpMM. Next, we propose a high performance systolic architecture for SpMM, which uses a mesh of comparators to locate the useful (non-zero) computation. This design maximizes data reuse by sharing the input data among a row/column of the mesh. We also show that, with similar memory access assumptions, the proposed architecture results in a 9-30 times speedup in comparison with the state of the art.
KW - CRS
KW - SpMM
KW - Sparse
KW - Systolic matrix multiplier
UR - http://www.scopus.com/inward/record.url?scp=85072622507&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85072622507&partnerID=8YFLogxK
U2 - 10.1109/ASAP.2019.00-28
DO - 10.1109/ASAP.2019.00-28
M3 - Conference contribution
AN - SCOPUS:85072622507
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 67
EP - 70
BT - Proceedings - 2019 IEEE 30th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2019
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 15 July 2019 through 17 July 2019
ER -