Sparse matrix to matrix multiplication: A representation and architecture for acceleration

Sharad Malik, Pareesa Ameneh Golnari

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Accelerators for sparse matrix multiplication are important components in emerging systems. In this paper, we study the main challenges of accelerating Sparse Matrix Multiplication (SpMM). For the situations that data is not stored in the desired order (row/column order), we propose a compact high performance sparse format, which allows for random access to a dataset with low memory access overhead. We show that using this format results in a 14-49 times speedup for SpMM. Next, we propose a high performance systolic architecture for SpMM, which uses a mesh of comparators to locate the useful (non-zero) computation. This design maximizes data reuse by sharing the input data among a row/column of the mesh. We also show that, with similar memory access assumptions, the proposed architecture results in a 9-30 times speedup in comparison with the state of the art.

Original languageEnglish (US)
Title of host publicationProceedings - 2019 IEEE 30th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages67-70
Number of pages4
ISBN (Electronic)9781728116013
DOIs
StatePublished - Jul 2019
Event30th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2019 - New York, United States
Duration: Jul 15 2019Jul 17 2019

Publication series

NameProceedings of the International Conference on Application-Specific Systems, Architectures and Processors
Volume2019-July
ISSN (Print)1063-6862

Conference

Conference30th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2019
CountryUnited States
CityNew York
Period7/15/197/17/19

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Computer Networks and Communications

Keywords

  • CRS
  • SpMM
  • Sparse
  • Systolic matrix multiplier

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  • Cite this

    Malik, S., & Golnari, P. A. (2019). Sparse matrix to matrix multiplication: A representation and architecture for acceleration. In Proceedings - 2019 IEEE 30th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2019 (pp. 67-70). [8825005] (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors; Vol. 2019-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASAP.2019.00-28