TY - GEN
T1 - Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC
AU - Arora, Divya
AU - Raghunathan, Anand
AU - Ravi, Srivaths
AU - Sankaradass, Murugan
AU - Jha, Niraj K.
AU - Chakradhar, Srimat T.
PY - 2006
Y1 - 2006
N2 - We present a systematic methodology for exploring the security processing software architecture for a commercial heterogeneous multiprocessor system-on-chip (SoC) for mobile devices. The SoC contains multiple host processors executing applications and a dedicated programmable security processing engine. We developed an exploration methodology to map the code and data of security software libraries onto the platform, with the objective of maximizing the overall application-visible performance. The salient features of the methodology include (i) the use of real performance measurements from a prototyping board that contains the target platform to drive the exploration, (ii) a new data structure access profiling framework that allows us to accurately model the communication overheads involved in offloading a given set of functions to the security processor, and (iii) an exact branch-and-bound based design space exploration algorithm that determines the best mapping of security library functions and data structures to the host and security processors.We used the proposed framework to map a commercial security library to the target mobile application SoC. The resulting optimized software architecture outperformed several manually-designed software architectures, resulting in upto 12.5X speedup for individual cryptographic operations (encryption, hashing) and 2.2X-6.2X speedup for applications such as a Digital Rights Management (DRM) agent and Secure Sockets Layer (SSL) client. We also demonstrate the applicability of our framework to software architecture exploration in other multiprocessor scenarios.
AB - We present a systematic methodology for exploring the security processing software architecture for a commercial heterogeneous multiprocessor system-on-chip (SoC) for mobile devices. The SoC contains multiple host processors executing applications and a dedicated programmable security processing engine. We developed an exploration methodology to map the code and data of security software libraries onto the platform, with the objective of maximizing the overall application-visible performance. The salient features of the methodology include (i) the use of real performance measurements from a prototyping board that contains the target platform to drive the exploration, (ii) a new data structure access profiling framework that allows us to accurately model the communication overheads involved in offloading a given set of functions to the security processor, and (iii) an exact branch-and-bound based design space exploration algorithm that determines the best mapping of security library functions and data structures to the host and security processors.We used the proposed framework to map a commercial security library to the target mobile application SoC. The resulting optimized software architecture outperformed several manually-designed software architectures, resulting in upto 12.5X speedup for individual cryptographic operations (encryption, hashing) and 2.2X-6.2X speedup for applications such as a Digital Rights Management (DRM) agent and Secure Sockets Layer (SSL) client. We also demonstrate the applicability of our framework to software architecture exploration in other multiprocessor scenarios.
KW - Computation offloading
KW - Software partitioning
UR - http://www.scopus.com/inward/record.url?scp=34547199653&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=34547199653&partnerID=8YFLogxK
U2 - 10.1145/1146909.1147040
DO - 10.1145/1146909.1147040
M3 - Conference contribution
AN - SCOPUS:34547199653
SN - 1595933816
SN - 1595933816
SN - 9781595933812
T3 - Proceedings - Design Automation Conference
SP - 496
EP - 501
BT - 2006 43rd ACM/IEEE Design Automation Conference, DAC'06
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 43rd Annual Design Automation Conference, DAC 2006
Y2 - 24 July 2006 through 28 July 2006
ER -