SISim: A system-level interactive simulator for array processor system

W. H. Chou, S. Y. Kung

Research output: Chapter in Book/Report/Conference proceedingConference contribution


A system-level simulation is critical to prevent designers from wasting time on the lower level design for an incorrect specification. It is also needed to evaluate the performance of the final implementation. In this paper, a system-level interactive simulator, SISim, for array processor system is proposed. The hardware and software specification modules for SISim are introduced. The simulation mechanism based on an event-driven scheme is discussed. The interactive mode of SISim is described. Then, an example for implementing a two-layer Back Propagation Neural Network on array processors is given. Some future work is also included.

Original languageEnglish (US)
Title of host publicationWorkshop on VLSI Signal Processing 1992
EditorsWojtek Przytula, Kung Yao, Rajeev Jain, Jan Rabaey
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages12
ISBN (Electronic)0780308115, 9780780308114
StatePublished - 1992
Event6th IEEE Workshop on VLSI Signal Processing - Los Angeles, United States
Duration: Oct 28 1992Oct 30 1992

Publication series

NameWorkshop on VLSI Signal Processing 1992


Conference6th IEEE Workshop on VLSI Signal Processing
Country/TerritoryUnited States
CityLos Angeles

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Electrical and Electronic Engineering
  • Applied Mathematics


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