Single-cycle bit permutations with MOMR execution

Ruby B. Lee, Xiao Yang, Zhi Jie Jerry Shi

Research output: Contribution to journalArticle

4 Scopus citations

Abstract

Secure computing paradigms impose new architectural challenges for general-purpose processors. Cryptographic processing is needed for secure communications, storage, and computations. We identify two categories of operations in symmetric-key and public-key cryptographic algorithms that are not common in previous general-purpose workloads: advanced bit operations within a word and multi-word operations. We define MOMR (Multiple Operands Multiple Results) execution or datarich execution as a unified solution to both challenges. It allows arbitrary n-bit permutations to be achieved in one or two cycles, rather than O(n) cycles as in existing RISC processors. It also enables significant acceleration of multi-word multiplications needed by public-key ciphers. We propose two implementations of MOMR: one employs only hardware changes while the other uses Instruction Set Architecture (ISA) support. We show that MOMR execution leverages available resources in typical multi-issue processors with minimal additional cost. Multi-issue processors enhanced with MOMR units provide additional speedup over standard multi-issue processors with the same datapath. MOMR is a general architectural solution for word-oriented processor architectures to incorporate datarich operations.

Original languageEnglish (US)
Pages (from-to)577-585
Number of pages9
JournalJournal of Computer Science and Technology
Volume20
Issue number5
DOIs
StatePublished - Sep 1 2005

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computer Science Applications
  • Computational Theory and Mathematics

Keywords

  • Bit permutations
  • Cryptographic acceleration
  • Cryptography
  • Datarich execution
  • High performance secure computing
  • ISA
  • Instruction set architecture
  • MOMR
  • Multi-word operation
  • Permutation
  • Processor
  • Security

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