Simultaneous dynamic voltage scaling of processors and communication links in real-time distributed embedded systems

Jiong Luo, Li Shiuan Peh, Niraj Kumar Jha

Research output: Contribution to journalConference article

19 Scopus citations

Abstract

Dynamic voltage scaling has been widely acknowledged as a powerful technique for trading off power consumption and delay for processors. Recently, variable-frequency (and variable-voltage) parallel and serial links have also been proposed, which can save link power consumption by exploiting variations in bandwidth requirement. In this paper, we address joint dynamic voltage scaling for variable-voltage processors and communication links in such systems. We propose a scheduling algorithm for real-time applications, with both data flow and control flow information captured. It performs efficient routing of communication events through multi-hops, as well as efficient slack allocation among heterogeneous processors and communication links to maximize energy savings, while meeting all real-time constraints.

Original languageEnglish (US)
Article number1253776
Pages (from-to)1150-1151
Number of pages2
JournalProceedings -Design, Automation and Test in Europe, DATE
DOIs
StatePublished - Dec 1 2003
EventDesign, Automation and Test in Europe Conference and Exhibition, DATE 2003 - Munich, Germany
Duration: Mar 3 2003Mar 7 2003

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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