Simulating Digital Circuits with One Bit Per Wire

Andrew W. Appel

doi:10.1109/43.7796

Simulating Digital Circuits with One Bit Per Wire

Andrew W. Appel

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

Conventional digital circuit simulators represent circuits using linked data structures, using one or more pointers per connection. To simulate a circuit of N nodes requires space proportional to N log N bits. Many circuits have a hierarchical or repetitive nature, so their specifications can be significantly smaller than the circuits themselves. This paper shows that such circuits can be simulated in space equal to one bit of memory per wire of the circuit, plus space proportional to the (smaller) size of the specification; that is, the space required is only O(N) bits. The algorithm has been implemented; measurements of its efficiency are given.

Original language	English (US)
Pages (from-to)	987-993
Number of pages	7
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	7
Issue number	9
DOIs	https://doi.org/10.1109/43.7796
State	Published - Sep 1988

All Science Journal Classification (ASJC) codes

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

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10.1109/43.7796

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abstract = "Conventional digital circuit simulators represent circuits using linked data structures, using one or more pointers per connection. To simulate a circuit of N nodes requires space proportional to N log N bits. Many circuits have a hierarchical or repetitive nature, so their specifications can be significantly smaller than the circuits themselves. This paper shows that such circuits can be simulated in space equal to one bit of memory per wire of the circuit, plus space proportional to the (smaller) size of the specification; that is, the space required is only O(N) bits. The algorithm has been implemented; measurements of its efficiency are given.",

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note = "Funding Information: Manuscript received April 29. 1987; revised November 17. 1987 and February 23. 1988. This work was supported in part by the National Science Foundation under Grant DCR-8603453 and in part by a Digital Equipment Corporation Faculty Incentive Grant. The review of thih paper was ;irrnnged by Associate Editor M. R. Lightner. Copyright: Copyright 2015 Elsevier B.V., All rights reserved.",

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N2 - Conventional digital circuit simulators represent circuits using linked data structures, using one or more pointers per connection. To simulate a circuit of N nodes requires space proportional to N log N bits. Many circuits have a hierarchical or repetitive nature, so their specifications can be significantly smaller than the circuits themselves. This paper shows that such circuits can be simulated in space equal to one bit of memory per wire of the circuit, plus space proportional to the (smaller) size of the specification; that is, the space required is only O(N) bits. The algorithm has been implemented; measurements of its efficiency are given.

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Simulating Digital Circuits with One Bit Per Wire

Abstract

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