Si Single-Electron MOS Memory With Nanoscale Floating-Gate and Narrow Channel

This paper presents the first single-electron MOS memories (SEMMs) having a narrow crystalline Si channel and a nanoscale poly-Si floating gate of a well controlled dimension. It reports that the behavior of the device can be explained by the single electron charging effect. First, since there is little oxide between the channel and the floating gate, the charging voltage primarily drops between the control gate and the floating gate. The capacitance for the 7 nm × 7 nm floating gate and a 40 nm control oxide is 4 × 10^-20 F, giving single electron charging voltage of 4V. Second, the shift in the SEMM's threshold voltage due to one electron stored into the floating gate, estimated from single-electron Debye screen length, 51 mV. And third, the self-limiting charging process comes from (a) raising of potential in the floating gate sue to single electron charging, (b) a large Coulomb energy level spacing, and (c) a thin barrier layer. All these estimations are consistent with the experiments.