Paths that are never exercised are referred to as false paths and timing analysis that ignores the delay contribution of these paths is referred to as functional timing analysis. Such timing analysis provides a more accurate estimate of circuit delay compared to conventional static timing analysis. We show how unmodified conventional Automatic Test Pattern Generators (ATPG) for stuck-at faults can be used for functional timing analysis without sacrificing computational efficiency in comparison with existing approaches to the same problem. This is a significant result since it enables us to use the entire body of work in ATPG for this problem and relieves us from re-inventing new solutions for this problem. The basic algorithm can be used under an arbitrary delay model. We provide delay computation results for all the ISCAS benchmark examples under the unit-delay and the mapped-delay models.
|Original language||English (US)|
|Number of pages||6|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|State||Published - Aug 1995|
All Science Journal Classification (ASJC) codes
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering