SHiP: Signature-based hit predictor for high performance caching

Carole Jean Wu, Aamer Jaleel, Will Hasenplaugh, Margaret Rose Martonosi, Simon C. Steely, Joel Emer

Research output: Chapter in Book/Report/Conference proceedingConference contribution

135 Scopus citations

Abstract

The shared last-level caches in CMPs play an important role in improving application performance and reducing off-chip memory bandwidth requirements. In order to use LLCs more efficiently, recent research has shown that changing the re-reference prediction on cache insertions and cache hits can significantly improve cache performance. A fundamental challenge, however, is how to best predict the re-reference pattern of an incoming cache line. This paper shows that cache performance can be improved by correlating the re-reference behavior of a cache line with a unique signature. We investigate the use of memory region, program counter, and instruction sequence history based signatures. We also propose a novel Signature-based Hit Predictor (SHiP) to learn the re-reference behavior of cache lines belonging to each signature. Overall, we find that SHiP offers substantial improvements over the baseline LRU replacement and state-of-the-art replacement policy proposals. On average, SHiP improves sequential and multiprogrammed application performance by roughly 10% and 12% over LRU replacement, respectively. Compared to recent replacement policy proposals such as Seg-LRU and SDBP, SHiP nearly doubles the performance gains while requiring less hardware overhead.

Original languageEnglish (US)
Title of host publicationMICRO 44 - Proceedings of the 44th Annual IEEE/ACM Symposium on Microarchitecture
Pages430-441
Number of pages12
DOIs
StatePublished - Dec 1 2011
Event44th Annual IEEE/ACM Symposium on Microarchitecture, MICRO 44 - Porto Alegre, RS, Brazil
Duration: Dec 4 2011Dec 7 2011

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
ISSN (Print)1072-4451

Other

Other44th Annual IEEE/ACM Symposium on Microarchitecture, MICRO 44
CountryBrazil
CityPorto Alegre, RS
Period12/4/1112/7/11

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Keywords

  • replacement
  • reuse distance prediction
  • shared cache

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