Shared last-level TLBs for chip multiprocessors

Abhishek Bhattacharjee, Daniel Lustig, Margaret Martonosi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

73 Scopus citations

Abstract

Translation Lookaside Buffers (TLBs) are critical to processor performance. Much past research has addressed uniprocessor TLBs, lowering access times and miss rates. However, as chip multiprocessors (CMPs) become ubiquitous, TLB design must be re-evaluated. This paper is the first to propose and evaluate shared last-level (SLL) TLBs as an alternative to the commercial norm of private, per-core L2 TLBs. SLL TLBs eliminate 7-79% of system-wide misses for parallel workloads. This is an average of 27% better than conventional private, per-core L2 TLBs, translating to notable runtime gains. SLL TLBs also provide benefits comparable to recently-proposed Inter-Core Cooperative (ICC) TLB prefetchers, but with considerably simpler hardware. Furthermore, unlike these prefetchers, SLL TLBs can aid sequential applications, eliminating 35-95% of the TLB misses for various multiprogrammed combinations of sequential applications. This corresponds to a 21% average increase in TLB miss eliminations compared to private, per-core L2 TLBs. Because of their benefits for parallel and sequential applications, and their readily-implementable hardware, SLL TLBs hold great promise for CMPs.

Original languageEnglish (US)
Title of host publicationProceedings - 17th International Symposium on High-Performance Computer Architecture, HPCA 2011
Pages62-73
Number of pages12
DOIs
StatePublished - May 17 2011
Event17th International Symposium on High-Performance Computer Architecture, HPCA 2011 - San Antonio, TX, United States
Duration: Feb 12 2011Feb 16 2011

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
ISSN (Print)1530-0897

Other

Other17th International Symposium on High-Performance Computer Architecture, HPCA 2011
CountryUnited States
CitySan Antonio, TX
Period2/12/112/16/11

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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  • Cite this

    Bhattacharjee, A., Lustig, D., & Martonosi, M. (2011). Shared last-level TLBs for chip multiprocessors. In Proceedings - 17th International Symposium on High-Performance Computer Architecture, HPCA 2011 (pp. 62-73). [5749717] (Proceedings - International Symposium on High-Performance Computer Architecture). https://doi.org/10.1109/HPCA.2011.5749717