Self-aligned imprint lithography for top-gate amorphous silicon thin-film transistor fabrication

E. Lausecker; Y. Huang; T. Fromherz; J. C. Sturm; S. Wagner

doi:10.1063/1.3457446

Self-aligned imprint lithography for top-gate amorphous silicon thin-film transistor fabrication

E. Lausecker, Y. Huang, T. Fromherz, J. C. Sturm, S. Wagner

Research output: Contribution to journal › Article › peer-review

25 Scopus citations

Abstract

We developed self-aligned imprint lithography (SAIL) for top-gate amorphous silicon (a-Si) thin-film transistors (TFTs). Our SAIL process enables a device pattern definition in a single imprint step that uses a three-level mold. The various levels of the mold are defined by a stepwise opening of a chromium hardmask and subsequent dry-etching. For TFT fabrication we imprint, and consecutively etch the imprint resist levels and device layers. The imprinted top-gate a-Si TFTs have nickel silicide source/drain self-aligned to the gate with mobilities of ∼0.4 cm2 /V s.

Original language	English (US)
Article number	263501
Journal	Applied Physics Letters
Volume	96
Issue number	26
DOIs	https://doi.org/10.1063/1.3457446
State	Published - Jun 28 2010

All Science Journal Classification (ASJC) codes

Physics and Astronomy (miscellaneous)

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10.1063/1.3457446

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title = "Self-aligned imprint lithography for top-gate amorphous silicon thin-film transistor fabrication",

abstract = "We developed self-aligned imprint lithography (SAIL) for top-gate amorphous silicon (a-Si) thin-film transistors (TFTs). Our SAIL process enables a device pattern definition in a single imprint step that uses a three-level mold. The various levels of the mold are defined by a stepwise opening of a chromium hardmask and subsequent dry-etching. For TFT fabrication we imprint, and consecutively etch the imprint resist levels and device layers. The imprinted top-gate a-Si TFTs have nickel silicide source/drain self-aligned to the gate with mobilities of ∼0.4 cm2 /V s.",

author = "E. Lausecker and Y. Huang and T. Fromherz and Sturm, {J. C.} and S. Wagner",

note = "Funding Information: This work was partially supported by the NILquantumdot project of the NILaustria project cluster (FFG project number 815803, www.nilaustria.at) through the Austrian NANO Initiative (bmvit and FFG, www.nanoinitiative.at). E.L. thanks the Austrian Fellowship Organizations of the University of Linz for financial support of her research stay and gratefully acknowledges the hospitality at Princeton University.",

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doi = "10.1063/1.3457446",

language = "English (US)",

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T1 - Self-aligned imprint lithography for top-gate amorphous silicon thin-film transistor fabrication

AU - Lausecker, E.

AU - Huang, Y.

AU - Fromherz, T.

AU - Sturm, J. C.

AU - Wagner, S.

N1 - Funding Information: This work was partially supported by the NILquantumdot project of the NILaustria project cluster (FFG project number 815803, www.nilaustria.at) through the Austrian NANO Initiative (bmvit and FFG, www.nanoinitiative.at). E.L. thanks the Austrian Fellowship Organizations of the University of Linz for financial support of her research stay and gratefully acknowledges the hospitality at Princeton University.

PY - 2010/6/28

Y1 - 2010/6/28

N2 - We developed self-aligned imprint lithography (SAIL) for top-gate amorphous silicon (a-Si) thin-film transistors (TFTs). Our SAIL process enables a device pattern definition in a single imprint step that uses a three-level mold. The various levels of the mold are defined by a stepwise opening of a chromium hardmask and subsequent dry-etching. For TFT fabrication we imprint, and consecutively etch the imprint resist levels and device layers. The imprinted top-gate a-Si TFTs have nickel silicide source/drain self-aligned to the gate with mobilities of ∼0.4 cm2 /V s.

AB - We developed self-aligned imprint lithography (SAIL) for top-gate amorphous silicon (a-Si) thin-film transistors (TFTs). Our SAIL process enables a device pattern definition in a single imprint step that uses a three-level mold. The various levels of the mold are defined by a stepwise opening of a chromium hardmask and subsequent dry-etching. For TFT fabrication we imprint, and consecutively etch the imprint resist levels and device layers. The imprinted top-gate a-Si TFTs have nickel silicide source/drain self-aligned to the gate with mobilities of ∼0.4 cm2 /V s.

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ER -

Self-aligned imprint lithography for top-gate amorphous silicon thin-film transistor fabrication

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