Security Verification via Automatic Hardware-Aware Exploit Synthesis: The CheckMate Approach

Caroline Trippel; Daniel Lustig; Margaret Rose Martonosi

doi:10.1109/MM.2019.2910010

Security Verification via Automatic Hardware-Aware Exploit Synthesis: The CheckMate Approach

Caroline Trippel, Daniel Lustig, Margaret Rose Martonosi

Research output: Contribution to journal › Article › peer-review

19 Scopus citations

Abstract

Many hardware security exploits result from the combination of well-known attack classes with newly exploited hardware features. CheckMate is an approach and automated tool for evaluating microarchitectural susceptibility to specified attack classes, and for synthesizing proof-of-concept exploit code for susceptible designs.

Original language	English (US)
Article number	8686197
Pages (from-to)	84-93
Number of pages	10
Journal	IEEE Micro
Volume	39
Issue number	3
DOIs	https://doi.org/10.1109/MM.2019.2910010
State	Published - May 1 2019

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/MM.2019.2910010

Cite this

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title = "Security Verification via Automatic Hardware-Aware Exploit Synthesis: The CheckMate Approach",

abstract = "Many hardware security exploits result from the combination of well-known attack classes with newly exploited hardware features. CheckMate is an approach and automated tool for evaluating microarchitectural susceptibility to specified attack classes, and for synthesizing proof-of-concept exploit code for susceptible designs.",

author = "Caroline Trippel and Daniel Lustig and Martonosi, {Margaret Rose}",

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Security Verification via Automatic Hardware-Aware Exploit Synthesis: The CheckMate Approach

Abstract

All Science Journal Classification (ASJC) codes

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