Scaling of the PARSEC benchmark inputs

Christian Bienia, Kai Li

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A good benchmark suite should provide users with inputs that have multiple levels of fidelity. We present a framework that takes the novel view that benchmark inputs should be considered approximations of their original, full-sized inputs. The paper demonstrates how to use the proposed methodology to create several simulation input sets for the PARSEC benchmarks and how to quantify and measure their approximation error. We offer guidelines that PARSEC users can use to choose suitable simulation inputs for their scientific studies in a way that maximizes the accuracy of the simulation subject to a time constraint.

Original languageEnglish (US)
Title of host publicationPACT'10 - Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages561-562
Number of pages2
ISBN (Print)9781450301787
DOIs
StatePublished - Jan 1 2010

Publication series

NameParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
Volume2010
ISSN (Print)1089-795X

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture

Keywords

  • benchmark suite
  • input reduction
  • multithreading
  • performance measurement
  • shared-memory computers
  • workload creation

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  • Cite this

    Bienia, C., & Li, K. (2010). Scaling of the PARSEC benchmark inputs. In PACT'10 - Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques (pp. 561-562). (Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT; Vol. 2010). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/1854273.1854352