Scaling datacenter accelerators with compute-Reuse architectures

Adi Fuchs, David Wentzlaff

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

Hardware specialization is commonly used in datacenters to ameliorate the nearing end of CMOS technology scaling. While offering superior performance and energy-efficiency returns compared to general-purpose processors, specialized accelerators are bound to the same device technology constraints, and are thus prone to similar limitations in the future. Once technology scaling plateaus, accelerator and application tuning will reach a point of near-optimum, with no clear direction for further improvements. Emerging non-volatile memory (NVM) technologies follow different scaling trends due to different physical properties and manufacturing techniques. NVMs have inspired recent efforts of innovation in computer systems, as they possess appealing qualities such as high capacity and low energy. We present the COmpute-REuse Accelerators (COREx) architecture that shifts computations from the scalability-hindered transistor-based logic towards the continuing-to-scale storage domain. COREx leverages datacenter redundancy by integrating a storage layer together with the accelerator processing layer. The added layer stores the outcomes of previous accelerated computations. The previously computed results are reused in the case of recurring computations, thus eliminating the need to re-compute them. We designed COREx as a combination of an accelerator and specialized storage layer using emerging memory technologies, and evaluated it on a set of datacenter workloads. Our results show that, when integrated with a well-tuned accelerator, COREx achieves an average speedup of 6.4× and average savings of 50% in energy and 68% in energy-delay product. We expect further increase in gains in the future, as memory technologies continue to improve steadily.

Original languageEnglish (US)
Title of host publicationProceedings - 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture, ISCA 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages353-366
Number of pages14
ISBN (Electronic)9781538659847
DOIs
StatePublished - Jul 19 2018
Event45th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2018 - Los Angeles, United States
Duration: Jun 2 2018Jun 6 2018

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897

Other

Other45th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2018
CountryUnited States
CityLos Angeles
Period6/2/186/6/18

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Keywords

  • Accelerators
  • Emerging memories
  • Memoization

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