Scaling application performance on a cache-coherent multiprocessors

Dongming Jiang, Jaswinder Pal Singh

Research output: Contribution to journalConference article

26 Scopus citations

Abstract

Hardware-coherent, distributed shared address space systems are increasingly successful at moderate scale. However, it is unclear whether, or with how much difficulty, the performance of a load-store shared address space programming model scales to large processor counts on real applications. We examine this question using an aggressive case-study machine, the SGI Origin2000, up to 128 processors. We show for the first time that scalable performance can indeed be achieved in this programming model on a wide range of applications, including challenging kernels like FFT. However, this does not come easily, even for applications considered to be already highly optimized, and is very often not simply a matter of increasing problem size. Rather, substantial further application restructuring is often needed, which is usually quite algorithmic in nature. We examine how the restructurings compare with those needed for performance portability to shared virtual memory on clusters, and we comment on common programming guidelines for performance portability and scalability as well as on how the programming difficulty compares with that of explicit message passing. We also examine where applications spend their time on this large machine, the impact of special hardware features that the machine provides, and the impact of mapping to the network topology.

Original languageEnglish (US)
Pages (from-to)305-316
Number of pages12
JournalConference Proceedings - Annual International Symposium on Computer Architecture, ISCA
StatePublished - Jan 1 1999
EventProceedings of the 1999 26th Annual International Symposium on Computer Architecture - ISCA '99 - Atlanta, GA, USA
Duration: May 2 1999May 4 1999

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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