Scalable hardware priority queue architectures for high-speed packet switches

Computer Science

• Existing Architecture 100%
• Good Performance 100%
• Hardware Solution 100%
• Multiple Connection 100%
• Verilog 100%

Keyphrases

• Hardware Solution 20%
• High-speed Links 20%
• Link Scheduling 20%
• Multiple Connections 20%
• Number of Connections 20%
• Number of Packets 20%
• Packet Size 20%
• Physical Link 20%
• Priority Level 20%
• Priority Queue 100%
• Queue Design 20%
• Scheduler 20%
• Small Packets 20%
• Verilog HDL 20%