Scalable hardware priority queue architectures for high-speed packet switches

Mathematics

• Priority Queue 100%
• High Speed 85%
• Hardware 85%
• Architecture 77%
• Switch 75%
• Systolic Array 40%
• Chip 35%
• Packet Scheduling 27%
• Design 26%
• Requirements 22%
• Quality of Service 21%
• Hardware Implementation 21%
• Performance Metrics 21%
• Shared Memory 20%
• Silicon 19%
• Encoder 18%
• Compiler 18%
• Efficient Implementation 16%
• Comparison Result 16%
• Simulation Experiment 15%
• Binary Tree 15%
• Trade-offs 14%
• Decrease 12%
• Output 10%
• Language 10%
• Necessary 9%
• Range of data 8%

Engineering & Materials Science

• Systolic arrays 60%
• Shift registers 58%
• Switches 50%
• Computer hardware description languages 49%
• Computer hardware 40%
• Binary trees 28%
• Data storage equipment 28%
• Transistors 19%
• Clocks 19%
• Silicon 18%
• Quality of service 18%
• Scheduling 16%
• Experiments 8%