Scalable hardware priority queue architectures for high-speed packet switches

Keyphrases

• Queuing Performance 40%
• Efficient Hardware Implementation 40%
• Low Memory Requirement 40%
• Queue Size 40%
• First-in-first-out 40%
• Loading Area 40%
• Scheduling Mechanism 40%
• Shared Memory Switch 40%
• Priority Encoder 40%

Computer Science

• First-in-First-Out 100%
• Scheduling Mechanism 100%
• Shared Memory Switch 100%